HomeSort by relevance Sort by last modified time
    Searched refs:SchedWrites (Results 1 - 2 of 2) sorted by null

  /external/llvm/utils/TableGen/
CodeGenSchedule.h 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
241 std::vector<CodeGenSchedRW> SchedWrites;
319 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
320 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
321 return SchedWrites[Idx];
CodeGenSchedule.cpp 100 // defined, and populate SchedReads and SchedWrites vectors. Implicit
206 SchedWrites.resize(1);
281 SchedWrites.emplace_back(SchedWrites.size(), *SWI);
289 for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(),
290 WE = SchedWrites.end(); WI != WE; ++WI) {
307 for (unsigned WIdx = 0, WEnd = SchedWrites.size(); WIdx != WEnd; ++WIdx) {
309 SchedWrites[WIdx].dump();
342 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
462 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
    [all...]

Completed in 56 milliseconds