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    Searched refs:SubReg0 (Results 1 - 6 of 6) sorted by null

  /external/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 214 unsigned SubReg0;
220 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
306 unsigned Src0 = 0, SubReg0;
313 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
350 SubReg0 = 0;
371 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 146 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
161 SubReg0 = SubReg2;
166 SubReg0 = SubReg1;
180 CommutedMI->getOperand(0).setSubReg(SubReg0);
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]
ARMISelLowering.cpp     [all...]
  /external/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 364 SDValue RC, SubReg0, SubReg1;
371 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
375 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
380 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
    [all...]

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