| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyLowerBrUnless.cpp | 60 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
78 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break;
79 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break;
80 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break;
81 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break;
82 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break;
83 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break;
84 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break;
85 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break;
86 case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUHazardRecognizers.h | 28 const TargetInstrInfo &TII;
32 SPUHazardRecognizer(const TargetInstrInfo &TII);
|
| SPUFrameLowering.cpp | 94 const SPUInstrInfo &TII =
119 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
131 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
136 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
139 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
141 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
144 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
147 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 34 const R600InstrInfo *TII;
41 TII(nullptr) { }
60 int OpIdx = TII->getOperandIdx(*OldMI, Op);
63 TII->setImmOperand(*NewMI, Op, Val);
69 TII = ST.getInstrInfo();
71 const R600RegisterInfo &TRI = TII->getRegisterInfo();
82 if (TII->isLDSRetInstr(MI.getOpcode())) {
83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
86 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
89 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode()
[all...] |
| SIShrinkInstructions.cpp | 80 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
84 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
97 TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
106 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
108 TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
115 if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
119 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
122 return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);
129 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
135 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI))
[all...] |
| R600EmitClauseMarkers.cpp | 38 const R600InstrInfo *TII;
56 if (TII->isLDSRetInstr(MI.getOpcode()))
59 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) ||
60 TII->isReductionOp(MI.getOpcode()))
75 if (TII->isALUInstr(MI.getOpcode()))
77 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()))
123 if (!TII->isALUInstr(MI.getOpcode()) && MI.getOpcode() != AMDGPU::DOT_4)
127 TII->getSrcs(MI)
[all...] |
| R600Packetizer.cpp | 60 const R600InstrInfo *TII;
75 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
87 if (TII->isPredicated(*BI))
89 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
97 if (isTrans || TII->isTransOnly(*BI)) {
139 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]);
153 TII(ST.getInstrInfo()),
154 TRI(TII->getRegisterInfo()) {
172 if (TII->isVector(MI)
[all...] |
| R600ClauseMergePass.cpp | 48 const R600InstrInfo *TII;
77 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT))
84 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::Enabled))
90 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
109 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
113 if (CumuledInsts >= TII->getMaxAlusPerClause()) {
121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0);
123 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0);
125 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0);
137 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1)
[all...] |
| SIFoldOperands.cpp | 134 const SIInstrInfo *TII) {
135 if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
143 MI->setDesc(TII->get(AMDGPU::V_MAD_F32));
144 bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII);
149 MI->setDesc(TII->get(Opc));
162 bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1);
180 !TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1))
183 if (!TII->isOperandLegal(*MI, OpNo, OpToFold))
195 const SIInstrInfo *TII, const SIRegisterInfo &TRI,
217 const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 32 const SparcInstrInfo &TII =
55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
73 const SparcInstrInfo &TII =
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
|
| /external/llvm/lib/CodeGen/ |
| PostRAHazardRecognizer.cpp | 70 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
72 TII->CreateTargetPostRAHazardRecognizer(Fn));
87 TII->insertNoop(MBB, MachineBasicBlock::iterator(MI));
|
| XRayInstrumentation.cpp | 63 auto *TII = MF.getSubtarget().getInstrInfo();
65 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER));
73 if (T.isReturn() && T.getOpcode() == TII->getReturnOpcode()) {
77 TII->get(TargetOpcode::PATCHABLE_RET))
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64A53Fix835769.cpp | 81 const TargetInstrInfo *TII;
116 TII = F.getSubtarget().getInstrInfo();
127 const TargetInstrInfo *TII) {
140 if (S == PrevBB && !TII->analyzeBranch(*PrevBB, TBB, FBB, Cond) && !TBB &&
152 const TargetInstrInfo *TII) {
157 while ((FMBB = getBBFallenThrough(FMBB, TII))) {
168 const TargetInstrInfo *TII) {
172 MachineInstr *I = getLastNonPseudo(MBB, TII);
175 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
179 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 30 const R600InstrInfo *TII;
34 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
53 const R600RegisterInfo &TRI = TII->getRegisterInfo();
63 bool IsReduction = TII->isReductionOp(MI.getOpcode());
64 bool IsVector = TII->isVector(MI);
65 bool IsCube = TII->isCubeOp(MI.getOpcode());
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
157 TII->addFlag(NewMI, 0, Flags);
|
| SIRegisterInfo.h | 28 const TargetInstrInfo &TII;
30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 27 const ARMBaseInstrInfo &TII;
38 const ARMBaseInstrInfo &tii,
42 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 30 const TargetInstrInfo &TII;
50 PPCHazardRecognizer970(const TargetInstrInfo &TII);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 121 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
128 BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
129 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
130 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
144 const MipsInstrInfo &TII =
165 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
169 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
171 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
183 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
188 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO))
[all...] |
| MipsEmitGPRestore.cpp | 31 const TargetInstrInfo *TII;
35 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
67 BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
80 BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
|
| /external/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 38 const Mips16InstrInfo &TII =
56 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
61 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
76 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
81 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
90 const Mips16InstrInfo &TII =
99 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
104 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
162 const Mips16InstrInfo &TII =
164 const MipsRegisterInfo &RI = TII.getRegisterInfo()
[all...] |
| MipsHazardSchedule.cpp | 112 const MipsInstrInfo *TII = STI->getInstrInfo();
118 if (!TII->HasForbiddenSlot(*I))
124 !TII->SafeInForbiddenSlot(*getNextMachineInstr(std::next(I)))) {
131 !TII->SafeInForbiddenSlot(*getNextMachineInstr(Succ->begin()))) {
141 BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP)));
|
| MipsLongBranch.cpp | 174 const MipsInstrInfo *TII =
182 MBBInfos[I].Size += TII->GetInstSizeInBytes(*MI);
220 const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
222 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
223 const MCInstrDesc &NewDesc = TII->get(NewOpc);
264 const MipsInstrInfo *TII =
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
300 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
319 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
322 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 48 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
53 !(TII.getSubtarget().hasMuxedUnits() && LastMI->mayLoadOrStore()) &&
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
63 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
64 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 46 const MSP430InstrInfo &TII =
67 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
71 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP)
99 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
111 const MSP430InstrInfo &TII =
136 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP);
158 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP);
162 TII.get(MSP430::SUB16ri), MSP430::SP)
171 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
192 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo()
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaFrameLowering.cpp | 50 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
56 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
58 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29)
61 BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT))
82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
85 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
87 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
95 BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ))
98 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15)
108 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo()
[all...] |
