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Searched
refs:TimerBaseAddress
(Results
1 - 8
of
8
) sorted by null
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/DebugAgentTimerLib/
DebugAgentTimerLib.c
79
UINT32
TimerBaseAddress
;
86
TimerBaseAddress
= TimerBase (TimerNumber);
87
gTISR =
TimerBaseAddress
+ GPTIMER_TISR;
88
gTCLR =
TimerBaseAddress
+ GPTIMER_TCLR;
89
gTLDR =
TimerBaseAddress
+ GPTIMER_TLDR;
90
gTCRR =
TimerBaseAddress
+ GPTIMER_TCRR;
91
gTIER =
TimerBaseAddress
+ GPTIMER_TIER;
/device/linaro/bootloader/edk2/Omap35xxPkg/Library/DebugAgentTimerLib/
DebugAgentTimerLib.c
79
UINT32
TimerBaseAddress
;
86
TimerBaseAddress
= TimerBase (TimerNumber);
87
gTISR =
TimerBaseAddress
+ GPTIMER_TISR;
88
gTCLR =
TimerBaseAddress
+ GPTIMER_TCLR;
89
gTLDR =
TimerBaseAddress
+ GPTIMER_TLDR;
90
gTCRR =
TimerBaseAddress
+ GPTIMER_TCRR;
91
gTIER =
TimerBaseAddress
+ GPTIMER_TIER;
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/
TimerLib.c
33
UINT32
TimerBaseAddress
= TimerBase(Timer);
35
if ((MmioRead32 (
TimerBaseAddress
+ GPTIMER_TCLR) & TCLR_ST_ON) == 0) {
40
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TCRR, 0x00000000);
41
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TLDR, 0x00000000);
44
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
47
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
/device/linaro/bootloader/edk2/Omap35xxPkg/Library/Omap35xxTimerLib/
TimerLib.c
33
UINT32
TimerBaseAddress
= TimerBase(Timer);
35
if ((MmioRead32 (
TimerBaseAddress
+ GPTIMER_TCLR) & TCLR_ST_ON) == 0) {
40
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TCRR, 0x00000000);
41
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TLDR, 0x00000000);
44
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
47
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
/device/linaro/bootloader/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Sec/
Sec.c
50
UINT32
TimerBaseAddress
= TimerBase(Timer);
56
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TCRR, 0x00000000);
57
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TLDR, 0x00000000);
60
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
63
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
/device/linaro/bootloader/edk2/BeagleBoardPkg/Sec/
Sec.c
50
UINT32
TimerBaseAddress
= TimerBase(Timer);
56
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TCRR, 0x00000000);
57
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TLDR, 0x00000000);
60
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
63
MmioWrite32 (
TimerBaseAddress
+ GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/TimerDxe/
Timer.c
336
UINT32
TimerBaseAddress
;
343
TimerBaseAddress
= TimerBase (FixedPcdGet32(PcdOmap35xxArchTimer));
344
TISR =
TimerBaseAddress
+ GPTIMER_TISR;
345
TCLR =
TimerBaseAddress
+ GPTIMER_TCLR;
346
TLDR =
TimerBaseAddress
+ GPTIMER_TLDR;
347
TCRR =
TimerBaseAddress
+ GPTIMER_TCRR;
348
TIER =
TimerBaseAddress
+ GPTIMER_TIER;
/device/linaro/bootloader/edk2/Omap35xxPkg/TimerDxe/
Timer.c
336
UINT32
TimerBaseAddress
;
343
TimerBaseAddress
= TimerBase (FixedPcdGet32(PcdOmap35xxArchTimer));
344
TISR =
TimerBaseAddress
+ GPTIMER_TISR;
345
TCLR =
TimerBaseAddress
+ GPTIMER_TCLR;
346
TLDR =
TimerBaseAddress
+ GPTIMER_TLDR;
347
TCRR =
TimerBaseAddress
+ GPTIMER_TCRR;
348
TIER =
TimerBaseAddress
+ GPTIMER_TIER;
Completed in 2925 milliseconds