| /bionic/libc/kernel/uapi/linux/ |
| v4l2-dv-timings.h | 156 #define V4L2_DV_BT_DMT_1280X800P120_RB {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) \
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| /development/ndk/platforms/android-21/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /external/kernel-headers/original/uapi/linux/ |
| v4l2-dv-timings.h | 529 #define V4L2_DV_BT_DMT_1280X800P120_RB { \
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| /prebuilts/ndk/r10/platforms/android-21/arch-arm/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-21/arch-arm64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-21/arch-mips/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-21/arch-mips64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-21/arch-x86/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-21/arch-x86_64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-23/arch-arm/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-23/arch-arm64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-23/arch-mips/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-23/arch-mips64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-23/arch-x86/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r10/platforms/android-23/arch-x86_64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-21/arch-arm/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-21/arch-arm64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-21/arch-mips/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-21/arch-mips64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-21/arch-x86/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-21/arch-x86_64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-23/arch-arm/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-23/arch-arm64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-23/arch-mips/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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| /prebuilts/ndk/r11/platforms/android-23/arch-mips64/usr/include/linux/ |
| v4l2-dv-timings.h | 87 #define V4L2_DV_BT_DMT_1280X800P120_RB { .type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, V4L2_DV_FL_REDUCED_BLANKING) }
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