| /external/clang/test/CXX/concepts-ts/dcl.dcl/dcl.spec/dcl.spec.concept/ |
| p2.cpp | 5 template<typename T> concept constexpr bool VCC = true; // expected-error {{variable concept cannot be declared 'constexpr'}}
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 88 // is vcc. We should handle this the same way we handle vopc, by addding
185 if (Use.getReg() == AMDGPU::VCC) {
330 // VOPC instructions can only write to the VCC register. We can't
331 // force them to use VCC here, because this is only one register and
333 // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
335 // So, instead of forcing the instruction to write to VCC, we provide
336 // a hint to the register allocator to use VCC and then we we will run
337 // this pass again after RA and shrink it if it outputs to VCC
[all...] |
| SIInsertWaits.cpp | 464 // TODO: We could probably just look at explicit operands if we removed VCC /
548 // of vcc back to vcc.
552 } else if (!hasOutstandingLGKM() && I->modifiesRegister(AMDGPU::VCC, TRI)) {
554 // Whenever we store a value in vcc, the correct value of vccz is
570 // Restore the vccz bit. Any time a value is written to vcc, the vcc
572 // vcc and then writing it back to the register.
574 AMDGPU::VCC)
575 .addReg(AMDGPU::VCC);
[all...] |
| SILowerControlFlow.cpp | 19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
252 unsigned Vcc = MI.getOperand(1).getReg();
255 .addReg(Vcc);
323 unsigned Vcc = MI.getOperand(1).getReg();
327 .addReg(Vcc)
[all...] |
| AMDGPUISelDAGToDAG.cpp | [all...] |
| AMDGPUAsmPrinter.cpp | 349 case AMDGPU::VCC:
|
| SIInstrInfo.cpp | 402 if (DestReg == AMDGPU::VCC) {
404 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
[all...] |
| SIRegisterInfo.cpp | 48 ReservedSGPRCount = 6; // VCC, FLAT_SCRATCH, XNACK
53 ReservedSGPRCount = 2; // VCC
836 case AMDGPU::VCC:
840 default: llvm_unreachable("Invalid SubIdx for VCC"); break;
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUAsmPrinter.cpp | 80 if (reg == AMDGPU::VCC) {
|
| SIGenRegisterInfo.pl | 90 def VCC : SIReg<"VCC">;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
273 #Add VCC to SReg_64
275 push (@registers, 'VCC')
|
| SIISelLowering.cpp | 208 AMDGPU::VCC)
239 AMDGPU::VCC)
245 .addReg(AMDGPU::VCC)
286 /// VCC register. In the VALU context, VCC is a one bit register, but in the
287 /// SALU context the VCC is a 64-bit register (1-bit per thread). Since only
288 /// the SALU can perform operations on the VCC register, we need to promote
|
| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| AMDGPUDisassembler.cpp | 209 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
212 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
217 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
420 case 106: return createRegOperand(VCC);
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ppc64/ |
| prog.go | 135 // their CC, V, and VCC variants
173 // and VCC variants, respectively.
|
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ppc64/ |
| prog.go | 135 // their CC, V, and VCC variants
173 // and VCC variants, respectively.
|
| /external/clang/unittests/AST/ |
| CommentParser.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 775 .Case("vcc", AMDGPU::VCC)
810 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { Reg = AMDGPU::VCC; RegWidth = 2; return true; }
[all...] |
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 185 case AMDGPU::VCC:
186 O << "vcc";
|
