/art/runtime/arch/mips64/ |
registers_mips64.h | 125 W13 = 13,
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/art/runtime/arch/arm64/ |
registers_arm64.h | 87 W13 = 13,
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/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.h | 45 case AArch64::X13: return AArch64::W13; 85 case AArch64::W13: return AArch64::X13;
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/external/llvm/lib/Target/Hexagon/ |
HexagonRegisterInfo.cpp | 75 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
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/art/compiler/utils/mips64/ |
managed_register_mips64_test.cc | 178 reg = Mips64ManagedRegister::FromVectorRegister(W13); 185 EXPECT_EQ(W13, reg.AsVectorRegister()); 187 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W13)));
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assembler_mips64_test.cc | 202 vec_registers_.push_back(new mips64::VectorRegister(mips64::W13)); [all...] |
/external/clang/test/Misc/ |
diag-template-diffing.cpp | [all...] |
/art/compiler/utils/arm64/ |
managed_register_arm64_test.cc | [all...] |
/external/llvm/lib/Target/Hexagon/Disassembler/ |
HexagonDisassembler.cpp | 538 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; [all...] |
/external/llvm/test/MC/AArch64/ |
arm64-arithmetic-encoding.s | 106 add w12, w13, w14 108 add w12, w13, w14, lsl #12 113 ; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b] 115 ; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b] 120 sub w12, w13, w14 122 sub w12, w13, w14, lsl #12 127 ; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b] 129 ; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b] 134 adds w12, w13, w14 136 adds w12, w13, w14, lsl #1 [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
AArch64Disassembler.cpp | 404 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, [all...] |