| /art/compiler/optimizing/ |
| intrinsics_mips.cc | 262 __ Wsbh(out, in);
277 __ Wsbh(out, out);
284 // __ Wsbh(out, out);
325 __ Wsbh(out_lo, AT);
326 __ Wsbh(out_hi, TMP);
343 // __ Wsbh(out_hi, out_hi);
350 // __ Wsbh(out_lo, out_lo);
529 __ Wsbh(out, out);
[all...] |
| intrinsics_mips64.cc | 236 __ Wsbh(out, out);
319 __ Wsbh(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
353 __ Wsbh(out, out);
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.h | 252 void Wsbh(Register rd, Register rt); // R2+
[all...] |
| assembler_mips.cc | 579 void MipsAssembler::Wsbh(Register rd, Register rt) {
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | [all...] |
| assembler_mips64.h | 480 void Wsbh(GpuRegister rd, GpuRegister rt);
[all...] |
| assembler_mips64.cc | 452 void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) {
[all...] |
