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Searched
refs:__IO
(Results
1 - 8
of
8
) sorted by null
/system/extras/simpleperf/nonlinux_support/include/linux/
ioctl.h
17
#define
__IO
(type, nr)
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm4.h
249
#define
__IO
volatile /*!< Defines 'read / write' permissions */
365
__IO
uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
367
__IO
uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
369
__IO
uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
371
__IO
uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
373
__IO
uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
375
__IO
uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
398
__IO
uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
399
__IO
uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
400
__IO
uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Contro (…)
[
all
...]
core_cm3.h
203
#define
__IO
volatile /*!< Defines 'read / write' permissions */
318
__IO
uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
320
__IO
uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
322
__IO
uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
324
__IO
uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
326
__IO
uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
328
__IO
uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
351
__IO
uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
352
__IO
uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
353
__IO
uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Contro (…)
[
all
...]
core_sc300.h
203
#define
__IO
volatile /*!< Defines 'read / write' permissions */
318
__IO
uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
320
__IO
uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
322
__IO
uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
324
__IO
uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
326
__IO
uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
328
__IO
uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
351
__IO
uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
352
__IO
uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
353
__IO
uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Contro (…)
[
all
...]
core_cm7.h
264
#define
__IO
volatile /*!< Defines 'read / write' permissions */
380
__IO
uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
382
__IO
uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
384
__IO
uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
386
__IO
uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
388
__IO
uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
390
__IO
uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
413
__IO
uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
414
__IO
uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
415
__IO
uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Contro (…)
[
all
...]
core_sc000.h
203
#define
__IO
volatile /*!< Defines 'read / write' permissions */
317
__IO
uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
319
__IO
uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
321
__IO
uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
323
__IO
uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
326
__IO
uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
343
__IO
uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
344
__IO
uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
345
__IO
uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
346
__IO
uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register (…)
[
all
...]
core_cm0.h
198
#define
__IO
volatile /*!< Defines 'read / write' permissions */
311
__IO
uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
313
__IO
uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
315
__IO
uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
317
__IO
uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
320
__IO
uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
337
__IO
uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
339
__IO
uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
340
__IO
uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
341
__IO
uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register (…)
[
all
...]
core_cm0plus.h
208
#define
__IO
volatile /*!< Defines 'read / write' permissions */
322
__IO
uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
324
__IO
uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
326
__IO
uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
328
__IO
uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
331
__IO
uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
348
__IO
uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
350
__IO
uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
354
__IO
uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
355
__IO
uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register (…)
[
all
...]
Completed in 416 milliseconds