| /art/runtime/arch/mips64/ |
| asm_support_mips64.S | 88 .macro MINint dreg,rreg,sreg,creg
91 .ifc \dreg, \rreg
92 selnez \dreg, \rreg, \creg
95 seleqz \dreg, \sreg, \creg
98 or \dreg, \dreg, \creg
103 .macro MINs dreg,rreg,sreg
107 MINint \dreg, \rreg, \sreg, $at
112 .macro MINu dreg,rreg,sreg
116 MINint \dreg, \rreg, \sreg, $a
[all...] |
| /art/runtime/arch/mips/ |
| asm_support_mips.S | 132 .macro MINint dreg,rreg,sreg,creg
136 .ifc \dreg, \rreg
137 selnez \dreg, \rreg, \creg
140 seleqz \dreg, \sreg, \creg
143 or \dreg, \dreg, \creg
145 movn \dreg, \rreg, \creg
146 movz \dreg, \sreg, \creg
152 .macro MINs dreg,rreg,sreg
156 MINint \dreg, \rreg, \sreg, $a
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| am33-2.c | 89 dreg (func_arg *arg, insn_data *data) function
90 #define dreg(shiftlow, shifthigh) { dreg, { i1: shiftlow, i2: shifthigh } } macro
358 lparen, amreg (4), rparen, comma, dreg (0, 8), tick_random);
360 lparen, amreg (4), plus, rparen, comma, dreg (0, 8), tick_random);
362 lparen, spreg, rparen, comma, dreg (0, 8));
364 dreg (4, 9), comma, lparen, amreg (0), rparen, tick_random);
366 dreg (4, 9), comma, lparen, amreg (0), plus, rparen, tick_random);
368 dreg (4, 9), comma, lparen, spreg, rparen);
370 dreg (4, 9), comma, dreg (0, 8), tick_random)
[all...] |
| /system/core/libpixelflinger/arch-mips64/ |
| col32cb16blend.S | 17 .macro pixel dreg src f sR sG sB shift
48 addu \dreg,$t2,\sB
51 or \dreg,\dreg,$t0
52 or \dreg,\dreg,$t1
|
| t32cb16blend.S | 24 * blend one of 2 16bpp RGB pixels held in dreg selected by shift
27 * Assumes that the dreg data is little endian and that
34 .macro pixel dreg src fb shift
46 ext $t8,\dreg,\shift+6+5,5 # dst[\shift:15..11]
48 ext $a4,\dreg,\shift+5,6 # start green extraction dst[\shift:10..5]
61 ext $a4,\dreg,\shift,5 # start blue extraction dst[\shift:4..0]
|
| /system/core/libpixelflinger/arch-mips/ |
| col32cb16blend.S | 17 .macro pixel dreg src f sR sG sB shift
53 addu \dreg,$t6,\sB
56 or \dreg,\dreg,$t4
57 or \dreg,\dreg,$t5
58 andi \dreg, 0xffff
|
| t32cb16blend.S | 25 * blend one of 2 16bpp RGB pixels held in dreg selected by shift
28 * Assumes that the dreg data is little endian and that
36 .macro pixel dreg src fb shift
52 ext $t8,\dreg,\shift+6+5,5 # dst[\shift:15..11]
54 ext $t0,\dreg,\shift+5,6 # start green extraction dst[\shift:10..5]
67 ext $t0,\dreg,\shift,5 # start blue extraction dst[\shift:4..0]
94 .macro pixel dreg src fb shift
119 srl $t8,\dreg,\shift+6+5
141 srl $t8,\dreg,\shift+5
153 srl $t8,\dreg,\shif
[all...] |
| /external/v8/src/ppc/ |
| simulator-ppc.h | 186 void set_d_register_from_double(int dreg, const double dbl) {
187 DCHECK(dreg >= 0 && dreg < kNumFPRs);
188 *bit_cast<double*>(&fp_registers_[dreg]) = dbl;
190 double get_double_from_d_register(int dreg) {
191 DCHECK(dreg >= 0 && dreg < kNumFPRs);
192 return *bit_cast<double*>(&fp_registers_[dreg]);
194 void set_d_register(int dreg, int64_t value) {
195 DCHECK(dreg >= 0 && dreg < kNumFPRs)
[all...] |
| deoptimizer-ppc.cc | 130 const DoubleRegister dreg = DoubleRegister::from_code(code); local
132 __ stfd(dreg, MemOperand(sp, offset));
275 const DoubleRegister dreg = DoubleRegister::from_code(code); local
277 __ lfd(dreg, MemOperand(r4, src_offset));
|
| /external/v8/src/arm/ |
| simulator-arm.h | 147 void set_dw_register(int dreg, const int* dbl);
150 void get_d_register(int dreg, uint64_t* value);
151 void set_d_register(int dreg, const uint64_t* value);
152 void get_d_register(int dreg, uint32_t* value);
153 void set_d_register(int dreg, const uint32_t* value);
162 void set_d_register_from_double(int dreg, const double& dbl) {
163 SetVFPRegister<double, 2>(dreg, dbl);
166 double get_double_from_d_register(int dreg) {
167 return GetFromVFPRegister<double, 2>(dreg);
|
| simulator-arm.cc | 868 void Simulator::set_dw_register(int dreg, const int* dbl) {
869 DCHECK((dreg >= 0) && (dreg < num_d_registers));
870 registers_[dreg] = dbl[0];
871 registers_[dreg + 1] = dbl[1];
875 void Simulator::get_d_register(int dreg, uint64_t* value) {
876 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
877 memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value));
881 void Simulator::set_d_register(int dreg, const uint64_t* value)
[all...] |
| /external/v8/src/arm64/ |
| simulator-arm64.cc | 176 return dreg(0);
672 TraceSim("Arguments: %f, %f\n", dreg(0), dreg(1));
673 int64_t result = target(dreg(0), dreg(1));
687 TraceSim("Argument: %f\n", dreg(0));
688 double result = target(dreg(0));
702 TraceSim("Arguments: %f, %f\n", dreg(0), dreg(1));
703 double result = target(dreg(0), dreg(1))
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm_toIR.c | 693 /* Plain ("low level") read from a VFP Dreg. */
700 /* Architected read from a VFP Dreg. */
705 /* Plain ("low level") write to a VFP Dreg. */
713 /* Architected write to a VFP Dreg. Handles conditional writes to the
736 /* Plain ("low level") read from a Neon Integer Dreg. */
743 /* Architected read from a Neon Integer Dreg. */
748 /* Plain ("low level") write to a Neon Integer Dreg. */
756 /* Architected write to a Neon Integer Dreg. Handles conditional
2859 UInt dreg = get_neon_d_regno(theInstr); local
2908 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); local
2988 UInt dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); local
3042 UInt dreg = get_neon_d_regno(theInstr); local
4834 UInt dreg = get_neon_d_regno(theInstr); local
5247 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); local
5913 UInt dreg = get_neon_d_regno(theInstr); local
6628 UInt dreg = get_neon_d_regno(theInstr); local
7648 UInt dreg = get_neon_d_regno(theInstr); local
[all...] |
| /external/vixl/test/aarch32/ |
| test-utils-aarch32.h | 177 const DRegister& dreg);
182 bool EqualFP32(float expected, const RegisterDump* core, const SRegister& dreg);
185 const DRegister& dreg);
|
| test-utils-aarch32.cc | 145 const DRegister& dreg) {
146 return Equal64(expected, core, core->GetDRegisterBits(dreg.GetCode()));
236 const DRegister& dreg) {
238 uint64_t result = core->GetDRegisterBits(dreg.GetCode());
|
| /external/v8/src/s390/ |
| simulator-s390.h | 163 void set_d_register_from_double(int dreg, const double dbl) {
164 DCHECK(dreg >= 0 && dreg < kNumFPRs);
165 *bit_cast<double*>(&fp_registers_[dreg]) = dbl;
168 double get_double_from_d_register(int dreg) {
169 DCHECK(dreg >= 0 && dreg < kNumFPRs);
170 return *bit_cast<double*>(&fp_registers_[dreg]);
172 void set_d_register(int dreg, int64_t value) {
173 DCHECK(dreg >= 0 && dreg < kNumFPRs)
[all...] |
| deoptimizer-s390.cc | 122 const DoubleRegister dreg = DoubleRegister::from_code(code); local
124 __ StoreDouble(dreg, MemOperand(sp, offset));
273 const DoubleRegister dreg = DoubleRegister::from_code(code); local
275 __ ld(dreg, MemOperand(r3, src_offset));
|
| /art/runtime/interpreter/mterp/arm/ |
| header.S | 168 .macro PREFETCH_ADVANCE_INST dreg, sreg, count
169 ldrh \dreg, [\sreg, #((\count)*2)]!
|
| /art/runtime/interpreter/mterp/arm64/ |
| header.S | 165 .macro PREFETCH_ADVANCE_INST dreg, sreg, count
166 ldrh \dreg, [\sreg, #((\count)*2)]!
|
| /external/vixl/test/aarch64/ |
| test-utils-aarch64.h | 112 inline double dreg(unsigned code) const { function in class:vixl::aarch64::RegisterDump
|
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 220 Arm64ManagedRegister dreg = Arm64ManagedRegister::FromDRegister(D0); local
226 EXPECT_TRUE(reg.Overlaps(dreg));
232 dreg = Arm64ManagedRegister::FromDRegister(D5);
238 EXPECT_TRUE(reg.Overlaps(dreg));
244 dreg = Arm64ManagedRegister::FromDRegister(D7);
250 EXPECT_TRUE(reg.Overlaps(dreg));
256 dreg = Arm64ManagedRegister::FromDRegister(D31);
262 EXPECT_TRUE(reg.Overlaps(dreg));
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| msp430-decode.opc | 359 opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
370 /** dopc sreg a b as dreg %D%b %1,%0 */
372 ID (dopc_to_id (dopc)); ASX (sreg, as, srxt_bits); ADX (dreg, a, dsxt_bits); ABW (al_bit, b);
393 /** 0001 00so c b ad dreg %S%b %1 */
395 ID (sopc_to_id (so,c)); ASX (dreg, ad, srxt_bits); ABW (al_bit, b);
|
| /external/vixl/test/aarch64/examples/ |
| test-examples.cc | 351 VIXL_CHECK(regs.dreg(0) == Add3DoubleC(A, B, C)); \
377 VIXL_CHECK(regs.dreg(0) == Add4DoubleC(A, B, C, D)); \
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Blur.S | 115 .macro vertfetch_noclamp i, dreg
121 umlal v12.4s, v16.4h, \dreg
122 umlal2 v13.4s, v16.8h, \dreg
124 umlal v14.4s, v11.4h, \dreg
126 umlal2 v15.4s, v11.8h, \dreg
137 .macro vertfetch_clamped i, dreg
147 umlal v12.4s, v16.4h, \dreg
148 umlal2 v13.4s, v16.8h, \dreg
150 umlal v14.4s, v11.4h, \dreg
152 umlal2 v15.4s, v11.8h, \dreg
[all...] |
| rsCpuIntrinsics_neon_Blur.S | 119 .macro vertfetch_noclamp i, dreg
128 vmlal.u16 q12, d20, \dreg
130 vmlal.u16 q13, d21, \dreg
131 vmlal.u16 q14, d22, \dreg
132 vmlal.u16 q15, d23, \dreg
143 .macro vertfetch_clamped i, dreg
154 vmlal.u16 q12, d20, \dreg
156 vmlal.u16 q13, d21, \dreg
158 vmlal.u16 q14, d22, \dreg
160 vmlal.u16 q15, d23, \dreg
[all...] |
