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    Searched refs:enableSubRegLiveness (Results 1 - 11 of 11) sorted by null

  /external/llvm/include/llvm/Target/
TargetSubtargetInfo.h 206 virtual bool enableSubRegLiveness() const { return false; }
  /external/llvm/lib/Target/Hexagon/
HexagonSubtarget.h 111 bool enableSubRegLiveness() const override;
HexagonSubtarget.cpp 56 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
131 bool HexagonSubtarget::enableSubRegLiveness() const {
132 return EnableSubregLiveness;
  /external/llvm/lib/Target/PowerPC/
PPCSubtarget.cpp 218 bool PPCSubtarget::enableSubRegLiveness() const {
PPCSubtarget.h 309 bool enableSubRegLiveness() const override;
  /external/llvm/lib/Target/AMDGPU/
AMDGPUSubtarget.h 289 bool enableSubRegLiveness() const override {
  /external/llvm/lib/CodeGen/
RenameIndependentSubregs.cpp 362 if (!MF.getSubtarget().enableSubRegLiveness())
DetectDeadLanes.cpp 580 if (!MF.getSubtarget().enableSubRegLiveness()) {
LiveIntervalAnalysis.cpp 61 static cl::opt<bool> EnableSubRegLiveness(
122 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
123 MRI->enableSubRegLiveness(true);
    [all...]
  /external/llvm/include/llvm/CodeGen/
MachineRegisterInfo.h 202 void enableSubRegLiveness(bool Enable = true) {
    [all...]
  /external/llvm/lib/CodeGen/MIRParser/
MIRParser.cpp 364 RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);

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