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    Searched refs:getSubRegs (Results 1 - 6 of 6) sorted by null

  /external/swiftshader/third_party/LLVM/utils/TableGen/
CodeGenRegisters.cpp 49 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
76 const SubRegMap &Map = SR->getSubRegs(RegBank);
80 // order getSubRegs is called on all registers.
115 const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
542 Registers[i]->getSubRegs(*this);
616 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
624 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
682 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
729 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
762 const CodeGenRegister::SubRegMap &SRM = (*RI)->getSubRegs();
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CodeGenRegisters.h 49 const SubRegMap &getSubRegs(CodeGenRegBank&);
51 const SubRegMap &getSubRegs() const {
RegisterInfoEmitter.cpp 284 if (Reg.getSubRegs().empty())
286 // getSubRegs() orders by SubRegIndex. We want a topological order.
321 if (!Reg.getSubRegs().empty())
723 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
744 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
  /external/llvm/lib/Target/Hexagon/
HexagonGenMux.cpp 89 void getSubRegs(unsigned Reg, BitVector &SRs) const;
108 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const {
116 getSubRegs(Reg, Set);
  /external/llvm/utils/TableGen/
CodeGenRegisters.cpp 353 // Initialize RegUnitList. Because getSubRegs is called recursively, this
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CodeGenRegisters.h 156 const SubRegMap &getSubRegs() const {
546 // Compute a weight for each register unit created during getSubRegs.

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