| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 1027 uint32_t imm9 = (unsigned)(simm) & 0x01FF; local
1028 return (0xB8 << 24) | (imm9 << 12) | (0x3 << 10) | (Rn << 5) | Rt;
1039 uint32_t imm9 = (unsigned)(simm) & 0x01FF; local
1041 (imm9 << 12) | (0x1 << 10) | (Rn << 5) | Rt;
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 456 void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) {
457 CHECK(IsInt<9>(imm9));
458 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x26);
461 void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) {
462 CHECK(IsInt<9>(imm9));
463 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x27);
466 void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) {
467 CHECK(IsInt<9>(imm9));
468 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x36);
471 void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) {
[all...] |
| assembler_mips64.h | 481 void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
482 void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); // MIPS64
483 void Ll(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
484 void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); // MIPS64
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 1115 Instr Assembler::ImmLS(int imm9) {
1116 DCHECK(is_int9(imm9));
1117 return truncate_to_int9(imm9) << ImmLS_offset;
[all...] |
| assembler-arm64.h | [all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| nds32.h | 118 #define N16_TYPE9(op6, imm9) \
119 (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9))
|
| /art/compiler/utils/mips/ |
| assembler_mips.cc | 755 void MipsAssembler::LlR6(Register rt, Register base, int16_t imm9) {
757 CHECK(IsInt<9>(imm9));
758 DsFsmInstrRrr(EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x36), rt, base, base);
761 void MipsAssembler::ScR6(Register rt, Register base, int16_t imm9) {
763 CHECK(IsInt<9>(imm9));
764 DsFsmInstrRrr(EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x26), rt, rt, base);
[all...] |
| assembler_mips.h | 290 void LlR6(Register rt, Register base, int16_t imm9 = 0);
291 void ScR6(Register rt, Register base, int16_t imm9 = 0);
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | 4711 UInt imm9 = INSN(20,12); local
5094 UInt imm9 = INSN(20,12); local
5172 UInt imm9 = INSN(20,12); local
5555 UInt imm9 = INSN(20,12); local
5601 UInt imm9 = INSN(20,12); local
[all...] |
