| /packages/apps/Messaging/src/com/android/messaging/util/ |
| CubicBezierInterpolator.java | 58 float ip0 = linearInterpolate(0, p1, t); local
63 ip0 = linearInterpolate(ip0, ip1, t);
67 return linearInterpolate(ip0, ip1, t);
|
| /art/compiler/linker/arm64/ |
| relative_patcher_arm64.cc | 381 __ Ldr(ip0.W(), lock_word);
385 __ Tbnz(ip0.W(), LockWord::kReadBarrierStateShift, slow_path);
397 __ Add(base_reg, base_reg, Operand(vixl::aarch64::ip0, LSR, 32));
414 assembler.JumpTo(ManagedRegister(arm64::X0), offset, ManagedRegister(arm64::IP0));
425 temps.Exclude(ip0, ip1);
438 __ Ldr(ip0.W(), ldr_address); // Load the LDR (immediate) unsigned offset.
439 __ Ubfx(ip0.W(), ip0.W(), 10, 12); // Extract the offset.
440 __ Ldr(ip0.W(), MemOperand(base_reg, ip0, LSL, 2)); // Load the reference
[all...] |
| /external/clang/test/CXX/temp/temp.arg/temp.arg.nontype/ |
| p1-11.cpp | 21 IP<0> ip0; // expected-error{{null non-type template argument must be cast to template parameter type 'int *'}} variable
|
| /external/v8/src/debug/arm64/ |
| debug-arm64.cc | 59 // ldr ip0, [pc, #(2 * kInstructionSize)]
60 // blr ip0
68 patcher.ldr_pcrel(ip0, (2 * kInstructionSize) >> kLoadLiteralScaleLog2);
76 patcher.blr(ip0);
|
| /external/clang/test/FixIt/ |
| fixit-cxx0x.cpp | 107 IP<0> ip0; // expected-error{{null non-type template argument must be cast to template parameter type 'int *'}} variable
|
| /external/vixl/examples/aarch64/ |
| custom-disassembler.cc | 41 AppendToOutput(reg.Is64Bits() ? "ip0" : "wip0");
122 __ Add(x11, ip0, ip1);
|
| /external/v8/src/arm64/ |
| deoptimizer-arm64.cc | 54 patcher.ldr_pcrel(ip0, (2 * kInstructionSize) >> kLoadLiteralScaleLog2);
55 patcher.blr(ip0);
|
| code-stubs-arm64.h | 43 static Register to_be_pushed_lr() { return ip0; }
|
| macro-assembler-arm64.cc | 46 return CPURegList(ip0, ip1);
[all...] |
| assembler-arm64.h | 313 ALIAS_REGISTER(Register, ip0, x16);
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | 316 tmp_list_(ip0, ip1),
337 tmp_list_(ip0, ip1),
356 tmp_list_(ip0, ip1),
[all...] |
| operands-aarch64.h | 465 const XRegister ip0 = x16;
|
| /art/compiler/optimizing/ |
| code_generator_arm64.cc | 692 // IP0 is used internally by the ReadBarrierMarkRegX entry point
694 DCHECK_NE(ref_.reg(), IP0);
[all...] |
| code_generator_arm64.h | 77 const vixl::aarch64::CPURegList vixl_reserved_core_registers(vixl::aarch64::ip0,
[all...] |
| intrinsics_arm64.cc | 197 // IP0 is used internally by the ReadBarrierMarkRegX entry point
200 DCHECK_NE(LocationFrom(src_curr_addr).reg(), IP0);
201 DCHECK_NE(LocationFrom(dst_curr_addr).reg(), IP0);
202 DCHECK_NE(LocationFrom(src_stop_addr).reg(), IP0);
203 DCHECK_NE(tmp_.reg(), IP0);
[all...] |
| /external/v8/src/builtins/arm64/ |
| builtins-arm64.cc | [all...] |
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 91 EXPECT_EQ(IP0, reg.AsXRegister());
627 EXPECT_TRUE(vixl::aarch64::ip0.Is(Arm64Assembler::reg_x(IP0)));
[all...] |
| /external/v8/src/full-codegen/arm64/ |
| full-codegen-arm64.cc | 472 __ ldr_pcrel(ip0, (3 * kInstructionSize) >> kLoadLiteralScaleLog2);
473 __ Add(current_sp, current_sp, ip0);
[all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | [all...] |
