| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb32.d | 208 0[0-9a-f]+ <[^>]+> ea70 0000 orns r0, r0, r0
209 0[0-9a-f]+ <[^>]+> ea75 0500 orns r5, r5, r0
210 0[0-9a-f]+ <[^>]+> ea70 0005 orns r0, r0, r5
211 0[0-9a-f]+ <[^>]+> ea70 0005 orns r0, r0, r5
212 0[0-9a-f]+ <[^>]+> ea75 0000 orns r0, r5, r0
218 0[0-9a-f]+ <[^>]+> ea70 0000 orns r0, r0, r0
[all...] |
| thumb32.s | 156 arit3 orn orns orn orns
|
| /external/valgrind/none/tests/arm/ |
| v6intThumb.stdout.exp | [all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb2-instructions.s | [all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.h | 485 virtual void orns(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { function in class:art::arm::ArmAssembler
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | [all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-rn-operand-const-t32.cc | 63 M(orns) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 63 M(orns) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 63 M(orns) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32.cc | 63 M(orns) \
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.cc | [all...] |
| assembler-aarch32.h | 2649 void orns(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.h | 823 void orns(Condition cond, Register rd, Register rn, const Operand& operand);
[all...] |
| disasm-aarch32.cc | 1999 void Disassembler::orns(Condition cond, function in class:vixl::aarch32::Disassembler
[all...] |
| assembler-aarch32.cc | 7085 void Assembler::orns(Condition cond, function in class:vixl::aarch32::Assembler
[all...] |
| macro-assembler-aarch32.h | [all...] |
