| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| tcompat.s | 19 shift ror rorls rors rorlss
|
| tcompat.d | 29 0+48 <[^>]*> e1b008e0 ? rors r0, r0, #17
|
| thumb32.d | [all...] |
| thumb-eabi.d | 33 0+02e <[^>]+> 41e1 rors r1, r4
|
| thumb.d | 34 0+02e <[^>]+> 41e1 rors r1, r4
|
| thumb32.s | 628 sh ror rors ror.w rors.w
|
| /bionic/libc/arch-arm/generic/bionic/ |
| strcpy.S | 83 rors r3, r3, #24
|
| /external/llvm/test/MC/ARM/ |
| thumb_rewrites.s | 89 rors r0, r0, r1
90 @ CHECK: rors r0, r1 @ encoding: [0xc8,0x41]
|
| basic-thumb-instructions.s | 486 rors r2, r7
488 @ CHECK: rors r2, r7 @ encoding: [0xfa,0x41]
|
| basic-thumb2-instructions.s | [all...] |
| /external/valgrind/none/tests/arm/ |
| v6intARM.stdout.exp | 322 RORS
323 rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000
324 rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 0, cpsr 0x80000000 N
325 rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000
326 rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000
327 rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000
328 rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000
329 rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000
330 rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000
331 rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000
[all...] |
| v6intThumb.stdout.exp | [all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb-instructions.s | 435 rors r2, r7
437 @ CHECK: rors r2, r7 @ encoding: [0xfa,0x41]
|
| basic-thumb2-instructions.s | [all...] |
| /external/vixl/src/aarch32/ |
| assembler-aarch32.h | 2825 void rors(Register rd, Register rm, const Operand& operand) { function in class:vixl::aarch32::Assembler
2828 void rors(Condition cond, Register rd, Register rm, const Operand& operand) { function in class:vixl::aarch32::Assembler
2831 void rors(EncodingSize size, function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.h | 893 void rors(Condition cond,
[all...] |
| disasm-aarch32.cc | 2289 void Disassembler::rors(Condition cond, function in class:vixl::aarch32::Disassembler
[all...] |
| assembler-aarch32.cc | 8215 void Assembler::rors(Condition cond, function in class:vixl::aarch32::Assembler
[all...] |
| macro-assembler-aarch32.h | [all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-rn-operand-rm-a32.cc | 85 M(rors)
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32.cc | 85 M(rors)
[all...] |
