| /external/libopus/celt/ |
| celt_encoder.c | 417 celt_sig * OPUS_RESTRICT out, int C, int CC, int LM, int upsample,
443 } while (++c<CC);
444 if (CC==2&&C==1)
463 int N, int CC, int upsample, const opus_val16 *coef, celt_sig *mem, int clip)
479 x = SCALEIN(pcmp[CC*i]);
494 inp[i*upsample] = SCALEIN(pcmp[CC*i]);
1065 static int run_prefilter(CELTEncoder *st, celt_sig *in, celt_sig *prefilter_mem, int CC, int N,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 151 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
236 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
303 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
304 if (CC == CallingConv::WebKit_JS)
306 if (CC == CallingConv::GHC)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 452 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
453 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
841 // MOVr can set CC.
[all...] |
| ARMFastISel.cpp | 188 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
196 CallingConv::ID CC,
201 const Instruction *I, CallingConv::ID CC,
252 // it needs default CC operands add those.
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 40 unsigned CC = ARMCC::AL;
42 CC = ITStates.back();
43 return CC;
638 unsigned CC;
639 CC = ITBlock.getITCC();
640 if (CC == 0xF)
641 CC = ARMCC::AL;
651 I = MI.insert(I, MCOperand::createImm(CC));
653 if (CC == ARMCC::AL)
661 I = MI.insert(I, MCOperand::createImm(CC));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 90 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
93 : CCState(CC, isVarArg, MF, locs, C),
268 return true; // CC didn't match.
443 return true; // CC didn't match.
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 130 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 168 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
179 X86::CondCode CC = X86::COND_INVALID;
184 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
186 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
188 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
190 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
192 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
193 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
194 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
195 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | 452 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
453 switch (CC) {
480 static bool InvertFPCondCode(Mips::CondCode CC) {
481 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
484 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
508 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
511 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
701 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
[all...] |
| /external/valgrind/callgrind/ |
| global.h | 181 typedef struct _CC CC;
848 void* CLG_(malloc)(const HChar* cc, UWord s, const HChar* f);
|
| /external/clang/lib/CodeGen/ |
| CGDebugInfo.cpp | 871 static unsigned getDwarfCC(CallingConv CC) {
872 switch (CC) {
[all...] |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| TargetLowering.cpp | 225 // Invert CC for unordered comparisons
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 503 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
504 switch (CC) {
531 /// conditional moves which use condition code CC should be inverted.
532 static bool invertFPCondCodeUser(Mips::CondCode CC) {
533 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
536 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
559 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
562 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32))
[all...] |
| /external/strace/ |
| Makefile | 457 COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
461 am__v_CC_0 = @echo " CC " $@;
463 CCLD = $(CC)
572 CC = gcc
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 279 } CC;
379 CC = o.CC;
452 return CC.Val;
[all...] |
| /art/compiler/optimizing/ |
| code_generator_arm.cc | [all...] |
| /external/clang/lib/Sema/ |
| SemaType.cpp | [all...] |
| /external/clang/tools/libclang/ |
| CIndex.cpp | [all...] |
