| /external/llvm/test/CodeGen/NVPTX/ |
| sext-in-reg.ll | 11 %conv1 = ashr exact i64 %sext, 56
13 %conv4 = ashr exact i64 %sext1, 56
14 %shr = ashr i64 %a, 16
15 %shr9 = ashr i64 %b, 16
29 %conv1 = ashr exact i64 %sext, 32
31 %conv4 = ashr exact i64 %sext1, 32
32 %shr = ashr i64 %a, 16
33 %shr9 = ashr i64 %b, 16
47 %conv1 = ashr exact i64 %sext, 48
49 %conv4 = ashr exact i64 %sext1, 4
[all...] |
| /external/llvm/test/Analysis/CostModel/X86/ |
| testshiftashr.ll | 8 ; SSE2: cost of 12 {{.*}} ashr
12 %0 = ashr %shifttype %a , %b
20 ; SSE2: cost of 16 {{.*}} ashr
24 %0 = ashr %shifttype4i16 %a , %b
32 ; SSE2: cost of 32 {{.*}} ashr
36 %0 = ashr %shifttype8i16 %a , %b
44 ; SSE2: cost of 64 {{.*}} ashr
48 %0 = ashr %shifttype16i16 %a , %b
56 ; SSE2: cost of 128 {{.*}} ashr
60 %0 = ashr %shifttype32i16 %a , %
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| field-extract-use-trunc.ll | 13 %tmp7.25 = ashr i32 %f11, 24
19 %tmp7.25 = ashr i32 %f11, 24
25 %tmp7.25 = ashr i64 %f11, 32
31 %tmp7.25 = ashr i16 %f11, 8
37 %tmp7.25 = ashr i16 %f11, 8
|
| ins_subreg_coalesce-2.ll | 5 %tmp7.25 = ashr i16 %f11, 8 ; <i16> [#uses=1]
|
| sar_fold.ll | 8 %2 = ashr exact i32 %1, 15
17 %2 = ashr exact i32 %1, 17
26 %2 = ashr exact i32 %1, 23
35 %2 = ashr exact i32 %1, 25
|
| sar_fold64.ll | 8 %2 = ashr exact i64 %1, 47
18 %2 = ashr exact i64 %1, 49
28 %2 = ashr exact i64 %1, 55
38 %2 = ashr exact i64 %1, 57
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| field-extract-use-trunc.ll | 13 %tmp7.25 = ashr i32 %f11, 24
19 %tmp7.25 = ashr i32 %f11, 24
25 %tmp7.25 = ashr i64 %f11, 32
31 %tmp7.25 = ashr i16 %f11, 8
37 %tmp7.25 = ashr i16 %f11, 8
|
| /external/llvm/test/Analysis/ValueTracking/ |
| known-power-of-two.ll | 14 %ashr = ashr exact i32 %trunc, 31
15 %div = sdiv i32 4, %ashr
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| apint-shift-simplify.ll | 2 ; RUN: egrep {shl|lshr|ashr} | count 3
19 %X = ashr i49 %A, %C
20 %Y = ashr i49 %B, %C
|
| 2004-02-23-ShiftShiftOverflow.ll | 5 %Y = ashr i32 %X, 17 ; <i32> [#uses=1]
6 %Z = ashr i32 %Y, 17 ; <i32> [#uses=1]
|
| /external/llvm/test/CodeGen/Hexagon/ |
| ashift-left-right.ll | 17 %shl1 = ashr i32 16, %a
18 %shl2 = ashr i32 %b, 16
|
| /external/llvm/test/CodeGen/SystemZ/ |
| int-neg-02.ll | 99 %ashr = ashr i64 %shl, 32
100 %neg = sub i64 0, %ashr
102 %abs = select i1 %cmp, i64 %neg, i64 %ashr
113 %ashr = ashr i64 %shl, 32
114 %neg = sub i64 0, %ashr
116 %abs = select i1 %cmp, i64 %neg, i64 %ashr
127 %ashr = ashr i64 %shl, 3
[all...] |
| int-abs-01.ll | 91 %ashr = ashr i64 %shl, 32
92 %neg = sub i64 0, %ashr
94 %abs = select i1 %cmp, i64 %neg, i64 %ashr
104 %ashr = ashr i64 %shl, 32
105 %neg = sub i64 0, %ashr
107 %abs = select i1 %cmp, i64 %neg, i64 %ashr
117 %ashr = ashr i64 %shl, 3
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| 2004-02-23-ShiftShiftOverflow.ll | 5 %Y = ashr i32 %X, 17 ; <i32> [#uses=1]
6 %Z = ashr i32 %Y, 17 ; <i32> [#uses=1]
|
| 2004-11-22-Missed-and-fold.ll | 5 %C = ashr i8 %A, 7 ; <i8> [#uses=1]
|
| 2006-02-13-DemandedMiscompile.ll | 6 %C = ashr i32 %B, 8 ; <i32> [#uses=1]
|
| /external/clang/test/CodeGen/ |
| exact-div-expr.c | 1 // RUN: %clang_cc1 -emit-llvm %s -o - -O1 | grep ashr
|
| /external/llvm/test/CodeGen/PowerPC/ |
| 2004-11-30-shr-var-crash.ll | 6 %tr2 = ashr i64 1, %shift.upgrd.1 ; <i64> [#uses=0]
|
| extsh.ll | 5 %tmp.82 = ashr i32 %tmp.81, 16 ; <i32> [#uses=1]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-asr.ll | 6 %tmp = ashr i32 %a, %b
|
| thumb2-asr2.ll | 6 %tmp = ashr i32 %a, 17
|
| /external/llvm/test/MC/Hexagon/ |
| inst_asrh.ll | 6 %1 = ashr i32 %a, 16
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
| 2004-11-30-shr-var-crash.ll | 6 %tr2 = ashr i64 1, %shift.upgrd.1 ; <i64> [#uses=0]
|
| extsh.ll | 5 %tmp.82 = ashr i32 %tmp.81, 16 ; <i32> [#uses=1]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| thumb2-asr.ll | 6 %tmp = ashr i32 %a, %b
|
