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  /external/llvm/test/CodeGen/SystemZ/
vec-abs-02.ll 119 %and1 = and <8 x i16> %shr, %neg
123 %ret = or <8 x i16> %and1, %and2
135 %and1 = and <8 x i16> %shr, %val
140 %ret = or <8 x i16> %and1, %and2
vec-abs-03.ll 118 %and1 = and <4 x i32> %shr, %neg
121 %ret = or <4 x i32> %and1, %and2
132 %and1 = and <4 x i32> %shr, %val
136 %ret = or <4 x i32> %and1, %and2
vec-abs-04.ll 118 %and1 = and <2 x i64> %shr, %neg
121 %ret = or <2 x i64> %and1, %and2
132 %and1 = and <2 x i64> %shr, %val
136 %ret = or <2 x i64> %and1, %and2
and-03.ll 129 %and1 = and i64 %and0, %val1
130 %and2 = and i64 %and1, %val2
asm-18.ll 330 %and1 = and i32 %res1, 65535
331 %or1 = or i32 %and1, 305397760
349 %and1 = and i32 %res1, 65535
350 %or1 = or i32 %and1, 305397760
454 %and1 = and i32 %res1, 268500991
455 %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %and1)
475 %and1 = and i32 %res1, 268500991
476 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %and1)
494 %and1 = and i32 %old, 14
497 "=h,r,r,0"(i32 %old, i32 %and1, i32 %and2
    [all...]
and-01.ll 164 %and1 = and i32 %and0, %val1
165 %and2 = and i32 %and1, %val2
insert-06.ll 174 %and1 = and i64 %a, 144115188075855872
176 %or = or i64 %and1, %and2
  /external/llvm/test/Transforms/InstCombine/
or-xor.ll 158 %and1 = and i32 %x, %noty
160 %xor = xor i32 %and1, %and2
169 %and1 = and i32 %or, 1
171 %xor = or i32 %and1, %and2
and2.ll 71 %and1 = and i1 %cmp1, %b
72 %and2 = and i1 %and1, %cmp2
bswap.ll 131 %and1 = and i32 %shr1, 255
134 %or = or i32 %and1, %shl1
  /art/test/565-checker-doublenegbitwise/src/
Main.java 281 /// CHECK: <<And1:i\d+>> And [<<Not1>>,<<Not2>>]
282 /// CHECK: <<Add:i\d+>> Add [<<And2>>,<<And1>>]
292 /// CHECK: <<And1:i\d+>> And [<<Not1>>,<<Not2>>]
293 /// CHECK: <<Add:i\d+>> Add [<<And2>>,<<And1>>]
  /art/test/646-checker-hadd-alt-byte/src/
Main.java 61 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<I255>>] loop:<<Loop>> outer_loop:none
63 /// CHECK-DAG: <<Add:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
111 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<I255>>] loop:<<Loop>> outer_loop:none
113 /// CHECK-DAG: <<Add1:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
  /art/test/646-checker-hadd-alt-char/src/
Main.java 61 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<IMAX>>] loop:<<Loop>> outer_loop:none
63 /// CHECK-DAG: <<Add:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
114 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<IMAX>>] loop:<<Loop>> outer_loop:none
116 /// CHECK-DAG: <<Add1:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
  /art/test/646-checker-hadd-alt-short/src/
Main.java 61 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<UMAX>>] loop:<<Loop>> outer_loop:none
63 /// CHECK-DAG: <<Add:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
111 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<UMAX>>] loop:<<Loop>> outer_loop:none
113 /// CHECK-DAG: <<Add1:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
  /art/test/646-checker-hadd-byte/src/
Main.java 58 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<I255>>] loop:<<Loop>> outer_loop:none
60 /// CHECK-DAG: <<Add:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
108 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<I255>>] loop:<<Loop>> outer_loop:none
110 /// CHECK-DAG: <<Add1:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
  /art/test/646-checker-hadd-char/src/
Main.java 58 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<IMAX>>] loop:<<Loop>> outer_loop:none
60 /// CHECK-DAG: <<Add:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
111 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<IMAX>>] loop:<<Loop>> outer_loop:none
113 /// CHECK-DAG: <<Add1:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
  /art/test/646-checker-hadd-short/src/
Main.java 58 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<UMAX>>] loop:<<Loop>> outer_loop:none
60 /// CHECK-DAG: <<Add:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
108 /// CHECK-DAG: <<And1:i\d+>> And [<<Get1>>,<<UMAX>>] loop:<<Loop>> outer_loop:none
110 /// CHECK-DAG: <<Add1:i\d+>> Add [<<And1>>,<<And2>>] loop:<<Loop>> outer_loop:none
  /external/llvm/test/CodeGen/AMDGPU/
and.ll 196 %and1 = and i64 %b, 549756338176
198 store volatile i64 %and1, i64 addrspace(1)* %out
230 %and1 = and i64 %shl.b, 62
232 %add1 = add i64 %and1, %c
275 %and1 = and i64 %b, 1231231234567
277 store volatile i64 %and1, i64 addrspace(1)* %out
296 %and1 = and i64 %b, 63
298 store volatile i64 %and1, i64 addrspace(1)* %out
  /external/llvm/test/CodeGen/ARM/
call-tc.ll 118 %and1 = and i32 %x, 2
119 %tobool2 = icmp eq i32 %and1, 0
  /external/llvm/test/CodeGen/X86/
bmi-intrinsics-fast-isel-x86_64.ll 106 %and1 = and i32 %a1, 255
109 %or = or i32 %and1, %shl
  /external/llvm/test/Transforms/InstSimplify/
reassociate.ll 14 define i32 @and1(i32 %x, i32 %y) {
15 ; CHECK-LABEL: @and1(
  /external/llvm/test/Transforms/WholeProgramDevirt/
virtual-const-prop-check.ll 89 ; CHECK: [[AND1:%[^ ]*]] = and i1 [[VTCMP1]], true
92 ; CHECK: ret i1 [[AND1]]
  /external/swiftshader/third_party/LLVM/test/Transforms/InstSimplify/
reassociate.ll 12 define i32 @and1(i32 %x, i32 %y) {
13 ; CHECK: @and1
  /external/llvm/test/CodeGen/AArch64/
tbz-tbnz.ll 133 %and1 = and i64 %val1, %val2
134 %tst1 = icmp slt i64 %and1, 0
  /external/llvm/test/Transforms/Reassociate/
xor_reassoc.ll 27 %and1 = and i32 %x, 456
28 %xor2 = xor i32 %xor, %and1

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