| /external/vixl/test/aarch32/config/ |
| cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| cond-rd-rn-operand-rm-shift-rs-a32.json | 34 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
|
| cond-rd-rn-operand-rm-t32.json | 66 "Ands", // ANDS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
67 // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| alias.d | 45 94: ea020020 ands x0, x1, x2
67 ec: 721d1f00 ands w0, w24, #0x7f8
|
| /external/libavc/encoder/arm/ |
| ih264e_evaluate_intra16x16_modes_a9q.s | 105 ands r7, r5, #01
109 ands r8, r5, #04
202 ands r7, r0, #01 @ vert mode valid????????????
206 ands r6, r0, #02 @ horz mode valid????????????
215 ands r6, r0, #04 @ dc mode valid????????????
|
| ih264e_evaluate_intra_chroma_modes_a9q.s | 264 ands r7, r0, #04 @ vert mode valid????????????
267 ands r6, r0, #02 @ horz mode valid????????????
270 ands r6, r0, #01 @ dc mode valid????????????
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
| metafpu21.d | 591 .*: 2c003321 F ANDS FX\.0,D0Re0,A0FrP
594 .*: 2c01e121 F ANDS FX\.0,D0\.7,RD
597 .*: 2c081f21 F ANDS FX\.1,D0Re0,D1\.7
600 .*: 2c09d121 F ANDS FX\.1,D0\.7,D1Re0
603 .*: 2c100f20 F ANDS FX\.2,D0Re0,D0\.7
606 .*: 2c11c721 F ANDS FX\.2,D0\.7,A1\.3
609 .*: 2c180321 F ANDS FX\.3,D0Re0,A1LbP
612 .*: 2c19c120 F ANDS FX\.3,D0\.7,D0Re0
615 .*: 2c19f521 F ANDS FX\.3,D0\.7,A0\.2
618 .*: 2c203321 F ANDS FX\.4,D0Re0,A0Fr
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/ArmV7/ |
| ArmV7Support.S | 215 ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
234 ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
239 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
|
| ArmV7Support.asm | 177 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
194 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
197 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
|
| /bionic/libc/arch-arm/cortex-a7/bionic/ |
| memset.S | 62 ands ip, r3, #7
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-early-ifcvt.ll | 325 ; CHECK: {{ands.*xzr,|tst}} w2, #0x80
343 ; CHECK: {{ands.*xzr,|tst}} x2, #0x8000000000000000
361 ; CHECK: {{ands.*xzr,|tst}} w2, #0x80
379 ; CHECK: {{ands.*xzr,|tst}} x2, #0x8000000000000000
|
| /external/llvm/test/CodeGen/PowerPC/ |
| rlwimi.ll | 1 ; All of these ands and shifts should be folded into rlwimi's
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
| rlwimi.ll | 1 ; All of these ands and shifts should be folded into rlwimi's
|
| /external/vixl/tools/ |
| verify_assembler_traces.py | 275 ("ands al {register} (\\1) (\\1)", "ands.n {}, {}, {}"),
276 ("ands al {register} {register} (\\1)", "ands.w {}, {}, {}"),
|
| /bionic/libc/arch-arm/denver/bionic/ |
| memmove.S | 76 ands r3, r0, #0x3f
262 ands ip, r2, #0x4
|
| /bionic/libc/arch-arm64/generic/bionic/ |
| string_copy.S | 108 ands tmp1, src, #15
228 ands has_nul1_w, has_nul1_w, #0x80808080
|
| strncmp.S | 73 ands tmp1, src1, #7
101 ands limit, limit, #7
|
| /device/google/contexthub/firmware/lib/libc/ |
| strlen.c | 96 "ands len, r0, #3\n\t"
140 "ands r2, r2, ip, lsl #7\n\t"
|
| /external/llvm/test/CodeGen/SystemZ/ |
| and-01.ll | 1 ; Test 32-bit ANDs in which the second operand is variable.
134 ; Check that ANDs of spilled values can use N rather than NR.
|
| /external/valgrind/none/tests/arm/ |
| v6intThumb.stdout.exp | 169 ANDS-16 0x100
170 ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 0, cpsr 0x00000000
171 ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
172 ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
173 ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
174 ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
175 ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
176 ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
177 ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 1, cpsr 0x10000000 V
178 ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z
[all...] |
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| strcmp.S | 191 ands ip, r0, #3
232 ands ip, r1, #3
398 ands r3, r3, b1, lsl #7
446 ands r3, r3, b1, lsl #7
491 ands r3, r3, b1, lsl #7
|
| /external/libavc/encoder/armv8/ |
| ih264e_evaluate_intra16x16_modes_av8.s | 110 ands w6, w5, #0x01
116 ands w6, w5, #0x04
476 ands w7, w0, #01 // vert mode valid????????????
480 ands w6, w0, #02 // horz mode valid????????????
483 ands w6, w0, #04 // dc mode valid????????????
|
| /bionic/libc/arch-arm/krait/bionic/ |
| strcmp.S | 191 ands ip, r0, #3
232 ands ip, r1, #3
410 ands r3, r3, b1, lsl #7
|
| /external/libavc/common/arm/ |
| ih264_intra_pred_chroma_a9q.s | 112 ands r2, r4, #0x01 @CHECKING IF LEFT_AVAILABLE ELSE BRANCHING TO ONLY TOP AVAILABLE
114 ands r2, r4, #0x04 @CHECKING IF TOP_AVAILABLE ELSE BRANCHING TO ONLY LEFT AVAILABLE
141 ands r2, r4, #0x04 @CHECKING TOP AVAILABILTY OR ELSE BRANCH TO NONE AVAILABLE
|
