| /toolchain/binutils/binutils-2.25/gas/config/ |
| xtensa-relax.h | 62 lower level, and the results then combined by logical ANDs at the
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| armv1.d | 12 0+04 <[^>]*> e0100000 ? ands r0, r0, r0
|
| /bionic/libc/arch-arm/cortex-a15/bionic/ |
| strcmp.S | 191 ands ip, r0, #3
232 ands ip, r1, #3
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| /bionic/libc/arch-arm/generic/bionic/ |
| memcpy.S | 80 ands r3, r3, #3
110 ands r3, r3, #0x1C
|
| /external/llvm/lib/Target/ARM/ |
| README-Thumb.txt | 143 ands r0, r3, r2, asl r0
168 2. It is sinking the shift of "1 << i" into the tst, and using ands instead of
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| /external/llvm/test/CodeGen/ARM/ |
| select_xform.ll | 253 ; T2: ands r0, {{r[0-9]+}}
268 ; T2: ands r0, {{r[0-9]+}}
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| thumb2-size-opt.ll | 7 ; CHECK-OPT: ands r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| README-Thumb.txt | 143 ands r0, r3, r2, asl r0
168 2. It is sinking the shift of "1 << i" into the tst, and using ands instead of
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| /external/v8/src/arm64/ |
| instructions-arm64.h | 250 // Of the logical (immediate) instructions, only ANDS (and its aliases)
254 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
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| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_inline.h | 217 ANDS x7, mask, x7, rrx;
401 "ands %1, %4, %1,rrx\n\t"
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| /packages/apps/UnifiedEmail/src/org/apache/commons/io/filefilter/ |
| FileFilterUtils.java | 96 * Returns a filter that ANDs the two specified filters.
100 * @return a filter that ANDs the two specified filters
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| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-asm-2.c | 165 value = 750; /* --> ands. */
175 value = 761; /* --> ands. */
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| /bionic/libc/arch-arm/bionic/ |
| setjmp.S | 213 ands r1, r1, #1
|
| /bionic/libc/arch-arm/denver/bionic/ |
| memcpy_base.S | 56 ands r3, r3, #0x3F
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| /bionic/libc/arch-arm64/generic/bionic/ |
| strchr.S | 86 ands tmp1, srcin, #31
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZTargetMachine.cpp | 163 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
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| /external/llvm/test/CodeGen/SystemZ/ |
| atomicrmw-nand-02.ll | 95 ; Check ANDs of 1. We AND the rotated word with 0x0001ffff.
|
| /external/minijail/ |
| bpf.c | 103 * On 64 bits, we have to do two 32-bit bitwise ANDs.
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_DecodeCoeffsToPair_s.s | 152 ANDS TrailingOnes, Symbol, #3
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_DecodeCoeffsToPair_s.s | 152 ANDS TrailingOnes, Symbol, #3
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_DecodeCoeffsToPair_s.S | 90 ANDS r1,r7,#3
|
| /external/arm-neon-tests/ |
| Init.s | 67 ANDS r3, r0, #&7000000
85 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
88 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
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| /external/libavc/common/arm/ |
| ih264_intra_pred_luma_4x4_a9q.s | 267 ands r5, r4, #0x01
278 ands r11, r4, #0x04 @ CHECKING IF TOP_AVAILABLE ELSE BRANCHING TO ONLY LEFT AVAILABLE
301 ands r11, r4, #0x04 @ CHECKING TOP AVAILABILTY OR ELSE BRANCH TO NONE AVAILABLE
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| ih264_intra_pred_luma_8x8_a9q.s | 352 ands r2, r4, #0x01 @CHECKING IF LEFT_AVAILABLE ELSE BRANCHING TO ONLY TOP AVAILABLE
354 ands r2, r4, #0x04 @CHECKING IF TOP_AVAILABLE ELSE BRANCHING TO ONLY LEFT AVAILABLE
369 ands r2, r4, #0x04 @CHECKING TOP AVAILABILTY OR ELSE BRANCH TO NONE AVAILABLE
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| /external/libavc/common/armv8/ |
| ih264_intra_pred_luma_4x4_av8.s | 268 ands w5, w4, #0x01
279 ands w11, w4, #0x04 // CHECKING IF TOP_AVAILABLE ELSE BRANCHING TO ONLY LEFT AVAILABLE
302 ands w11, w4, #0x04 // CHECKING TOP AVAILABILTY OR ELSE BRANCH TO NONE AVAILABLE
|
