/toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
metacore21.d | [all...] |
metacore21.s | [all...] |
/external/valgrind/none/tests/arm64/ |
integer.stdout.exp | 293 ands x3,x4, #0x8080808080808080 :: rd 8000808000000000 rn 843fdf810277796e, cin 0, nzcv 80000000 N 294 ands x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd c04040c080400000 rn c5446fe48c610b28, cin 0, nzcv 80000000 N 295 ands x3,x4, #0x8080808080808080 :: rd 0000808000000000 rn 143fdf810277796e, cin 0, nzcv 00000000 296 ands x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd 804040c080400000 rn a5446fe48c610b28, cin 0, nzcv 80000000 N 297 ands x3,x4, #0x8080808080808080 :: rd 0000000000000000 rn 7070707070707070, cin 0, nzcv 40000000 Z 298 ands x3,x4, #0x8080808080808080 :: rd 8000000000000000 rn f070707070707070, cin 0, nzcv 80000000 N 302 ands w3,w4, #0x80808080 :: rd 0000000000000000 rn 843fdf810277796e, cin 0, nzcv 40000000 Z 303 ands w3,w4, #0xC0C0C0C0 :: rd 0000000080400000 rn c5446fe48c610b28, cin 0, nzcv 80000000 N 304 ands w3,w4, #0x80808080 :: rd 0000000000000000 rn 143fdf810277796e, cin 0, nzcv 40000000 Z 305 ands w3,w4, #0xC0C0C0C0 :: rd 0000000080400000 rn a5446fe48c610b28, cin 0, nzcv 80000000 N [all...] |
/external/vixl/test/aarch32/ |
test-assembler-aarch32.cc | 552 TEST(ands) { 559 __ Ands(r0, r1, r1); 571 __ Ands(r0, r0, Operand(r1, LSL, 4)); 583 __ Ands(r0, r0, Operand(r1, LSR, 4)); 595 __ Ands(r0, r0, Operand(r1, ASR, 4)); 607 __ Ands(r0, r0, Operand(r1, ROR, 1)); 621 __ Ands(r2, r0, Operand(r1, RRX)); 636 __ Ands(r2, r0, Operand(r1, RRX)); 647 __ Ands(r0, r0, 0xf); 658 __ Ands(r0, r0, 0x80000000) [all...] |
/toolchain/binutils/binutils-2.25/include/opcode/ |
metag.h | [all...] |
/external/vixl/src/aarch64/ |
constants-aarch64.h | 539 ANDS = 0x60000000, 540 BICS = ANDS | NOT 554 ANDS_w_imm = LogicalImmediateFixed | ANDS, 555 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits 581 ANDS_w = LogicalShiftedFixed | ANDS, 582 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, [all...] |
instructions-aarch64.h | 346 // Of the logical (immediate) instructions, only ANDS (and its aliases) 350 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
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/external/libavc/common/armv8/ |
ih264_intra_pred_luma_8x8_av8.s | 297 ands w6, w4, #0x01 314 ands w11, w4, #0x04 // CHECKING IF TOP_AVAILABLE ELSE BRANCHING TO ONLY LEFT AVAILABLE 340 ands w11, w4, #0x04 // CHECKING TOP AVAILABILTY OR ELSE BRANCH TO NONE AVAILABLE
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ih264_intra_pred_luma_16x16_av8.s | 306 ands w6, w4, #0x01 312 ands w6, w4, #0x04
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/art/runtime/interpreter/mterp/arm/ |
footer.S | 159 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
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/external/aac/libFDK/include/arm/ |
scramble.h | 112 "ands r10, r4, r5;\n" /* r10 = r4 & r5; */
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/external/boringssl/src/crypto/des/ |
internal.h | 164 could be done in 15 xor, 10 shifts and 5 ands.
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/external/llvm/lib/Target/Hexagon/ |
HexagonTargetMachine.cpp | 229 // Replace certain combinations of shifts and ands with extracts.
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/external/llvm/test/CodeGen/SystemZ/ |
int-conv-02.ll | 26 ; Check ANDs that are equivalent to zero extension.
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int-conv-04.ll | 25 ; Check ANDs that are equivalent to zero extension.
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int-conv-06.ll | 26 ; Check ANDs that are equivalent to zero extension.
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int-conv-08.ll | 25 ; Check ANDs that are equivalent to zero extension.
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/external/llvm/test/CodeGen/X86/ |
machine-combiner-int.ll | 59 ; Verify that integer 'ands' are reassociated. The first 'and' in
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/external/tremolo/Tremolo/ |
asm_arm.h | 182 "ands r0,%5,#1;\n"
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 188 ANDS Temp3, Counter, #1
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/packages/apps/LegacyCamera/jni/feature_stab/src/dbreg/ |
dbstabsmooth.cpp | 150 // between 0.9 and 1.0, in steps of 0.01, and between 0.5 ands 0.9 in steps of 0.1
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/external/llvm/test/MC/AArch64/ |
arm64-diags.s | 270 ands w0, w0, w0, lsl #32 label 272 ; CHECK-ERRORS: ands w0, w0, w0, lsl #32
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
thumb32.s | 150 arit3 and ands and.w ands.w
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/external/v8/src/arm64/ |
macro-assembler-arm64-inl.h | 55 void MacroAssembler::Ands(const Register& rd, 60 LogicalMacro(rd, rn, operand, ANDS); 67 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS); [all...] |
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/AArch64/ |
AArch64Support.S | 406 ands x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
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