| /external/guava/guava-gwt/test-super/com/google/common/base/super/com/google/common/base/ |
| PredicatesTest.java | 602 // While not a contractual requirement, we'd like the hash codes for ands
|
| /external/llvm/include/llvm/Transforms/Utils/ |
| LoopUtils.h | 211 /// that ANDs the Phi with a type mask, return the user. RT is updated to
|
| /external/llvm/test/CodeGen/SystemZ/ |
| and-08.ll | 1 ; Test memory-to-memory ANDs.
|
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | [all...] |
| /external/vixl/src/aarch32/ |
| constants-aarch32.cc | 52 return "ands";
|
| assembler-aarch32.h | 1960 void ands(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
1963 void ands(Condition cond, Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
1966 void ands(EncodingSize size, function in class:vixl::aarch32::Assembler
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb-eabi.d | 26 0+020 <[^>]+> 402b ands r3, r5
|
| thumb.d | 27 0+020 <[^>]+> 402b ands r3, r5
|
| thumb32.d | 130 0[0-9a-f]+ <[^>]+> 4000 ands r0, r0
131 0[0-9a-f]+ <[^>]+> 4005 ands r5, r0
132 0[0-9a-f]+ <[^>]+> 4028 ands r0, r5
133 0[0-9a-f]+ <[^>]+> 4028 ands r0, r5
134 0[0-9a-f]+ <[^>]+> 4028 ands r0, r5
140 0[0-9a-f]+ <[^>]+> ea10 0000 ands\.w r0, r0, r0
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Blur.S | [all...] |
| rsCpuIntrinsics_neon_Blur.S | [all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | 698 void MacroAssembler::Ands(const Register& rd,
702 LogicalMacro(rd, rn, operand, ANDS);
708 Ands(AppropriateZeroRegFor(rn), rn, operand);
802 case ANDS:
821 case ANDS:
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| basic-a64-instructions.txt | [all...] |
| /external/v8/src/arm64/ |
| disasm-arm64.cc | 243 mnemonic = "ands";
304 mnemonic = "ands";
[all...] |
| assembler-arm64.cc | 1189 void Assembler::ands(const Register& rd, function in class:v8::internal::Assembler
[all...] |
| /external/vixl/test/aarch64/ |
| test-disasm-aarch64.cc | 791 COMPARE(ands(w23, w24, Operand(0x0000000f)), "ands w23, w24, #0xf");
792 COMPARE(ands(x25, x26, Operand(0x800000000000000f)),
793 "ands x25, x26, #0x800000000000000f");
[all...] |
| /art/compiler/optimizing/ |
| nodes_vector.h | 483 // Bitwise-ands every component in the two vectors,
|
| /external/guava/guava-tests/test/com/google/common/base/ |
| PredicatesTest.java | 910 // While not a contractual requirement, we'd like the hash codes for ands
[all...] |
| /external/libavc/common/armv8/ |
| ih264_intra_pred_chroma_av8.s | 119 ands w6, w4, w19
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 60 ANDS,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.td | [all...] |
| SystemZISelDAGToDAG.cpp | [all...] |
| /external/ltp/doc/ |
| style-guide.txt | 261 1. Always use libltp for Linux centric tests. No ifs, ands, or buts
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| illegal.s | 550 ands w0, w24, #0xffeefffffffffffd
|
