| /external/llvm/test/MC/AArch64/ |
| arm64-aliases.s | 43 ands wzr, w1, w2, lsl #2
44 ands xzr, x1, x2, lsl #3
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| basic-a64-diagnostics.s | [all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_T2_32.c | 100 #define ANDS 0x4000
757 return push_inst16(compiler, ANDS | RD3(dst) | RN3(arg2));
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-rn-operand-const-a32.cc | 57 M(ands) \
[all...] |
| test-assembler-cond-rd-rn-operand-const-t32.cc | 57 M(ands) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-a32.cc | 57 M(ands) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 57 M(ands) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 57 M(ands) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 57 M(ands) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 57 M(ands) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32.cc | 57 M(ands) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | 123 M(Ands) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-t32.cc | 123 M(Ands) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-a32.cc | 123 M(Ands) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 123 M(Ands) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 123 M(Ands) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 123 M(Ands) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 123 M(Ands) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-t32.cc | 123 M(Ands) \
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_ColorMatrix.S | [all...] |
| /toolchain/binutils/binutils-2.25/bfd/ |
| coff64-rs6000.c | 384 defined by shifts-and-ands, which are equivalent on all
473 defined by shifts-and-ands, which are equivalent on all
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.h | 412 virtual void ands(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { function in class:art::arm::ArmAssembler
[all...] |
| /external/boringssl/src/include/openssl/ |
| bio.h | 197 /* BIO_clear_flags ANDs |bio->flags| with the bitwise-complement of |flags|. */
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| README.txt | 336 We could collapse a bunch of those ORs and ANDs and generate the following
|
| /external/syslinux/com32/cmenu/libmenu/ |
| des.c | 136 * No E box is used, as it's replaced by some ANDs, shifts, and ORs.
|
