| /external/vixl/src/aarch64/ |
| assembler-aarch64.cc | 500 void Assembler::ands(const Register& rd, function in class:vixl::aarch64::Assembler
503 Logical(rd, rn, operand, ANDS);
508 ands(AppropriateZeroRegFor(rn), rn, operand);
[all...] |
| disasm-aarch64.cc | 278 mnemonic = "ands";
349 mnemonic = "ands";
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis-2.c | [all...] |
| /art/compiler/utils/ |
| assembler_thumb_test.cc | 265 __ ands(R0, R0, ShifterOperand(R1));
297 __ ands(R0, R0, ShifterOperand(R8));
318 __ ands(R0, R0, ShifterOperand(R1), arm::EQ);
[all...] |
| /external/valgrind/none/tests/arm64/ |
| integer.c | 491 TESTINST2("ands x3,x4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0);
492 TESTINST2("ands x3,x4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
493 TESTINST2("ands x3,x4, #0x8080808080808080", 0x143fdf810277796e, x3, x4, 0);
494 TESTINST2("ands x3,x4, #0xC0C0C0C0C0C0C0C0", 0xA5446fe48c610b28, x3, x4, 0);
495 TESTINST2("ands x3,x4, #0x8080808080808080", 0x7070707070707070, x3, x4, 0);
496 TESTINST2("ands x3,x4, #0x8080808080808080", 0xF070707070707070, x3, x4, 0);
501 TESTINST2("ands w3,w4, #0x80808080", 0x843fdf810277796e, x3, x4, 0);
502 TESTINST2("ands w3,w4, #0xC0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
503 TESTINST2("ands w3,w4, #0x80808080", 0x143fdf810277796e, x3, x4, 0);
504 TESTINST2("ands w3,w4, #0xC0C0C0C0", 0xA5446fe48c610b28, x3, x4, 0)
[all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | 821 TEST(ands) {
826 __ Ands(w0, w1, Operand(w1));
837 __ Ands(w0, w0, Operand(w1, LSR, 4));
848 __ Ands(x0, x0, Operand(x1, ROR, 1));
858 __ Ands(w0, w0, Operand(0xf));
868 __ Ands(w0, w0, Operand(0x80000000));
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| assembler-aarch32.cc | 2612 void Assembler::ands(Condition cond, function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.h | 516 void ands(Condition cond,
[all...] |
| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | [all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 57 M(ands) \
[all...] |
| /external/skia/src/opts/ |
| SkBlitRow_opts_arm_neon.cpp | 200 "ands ip, %[count], #7 \n\t"
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/gen/ |
| MIPS.rules | 571 // fold extensions and ANDs together
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/gen/ |
| MIPS.rules | 571 // fold extensions and ANDs together
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | 229 ands r3, r12, #0xf
233 ands r1, r9, #0xffffffff
236 @ CHECK: ands r3, r12, #15 @ encoding: [0x1c,0xf0,0x0f,0x03]
240 @ CHECK: ands r1, r9, #4294967295 @ encoding: [0x19,0xf0,0xff,0x31]
247 ands r2, r1, r7, lsl #1
248 ands.w r4, r5, r2, lsr #20
253 @ CHECK: ands.w r2, r1, r7, lsl #1 @ encoding: [0x11,0xea,0x47,0x02]
254 @ CHECK: ands.w r4, r5, r2, lsr #20 @ encoding: [0x15,0xea,0x12,0x54]
[all...] |
| /external/vixl/doc/aarch64/ |
| supported-instructions-aarch64.md | 85 ### ANDS ###
89 void ands(const Register& rd,
[all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_arm64.S | 657 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
680 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
703 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
728 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
[all...] |
| /external/libavc/encoder/arm/ |
| ime_distortion_metrics_a9q.s | 1024 ands r11, r8, #1 @II See if we are at even or odd block
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| README.txt | 584 We could collapse a bunch of those ORs and ANDs and generate the following
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| xtensa-relax.c | [all...] |
| /toolchain/binutils/binutils-2.25/gas/ |
| expr.c | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 476 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
728 // ANDS does not use the same encoding scheme as the others xxxS
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | 600 // Look for ANDs in the LHS icmp.
656 // Look for ANDs on the right side of the RHS icmp.
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64.cc | 96 case ANDS: // Fall through.
114 case ANDS: // Fall through.
[all...] |
