| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 123 M(Ands) \
[all...] |
| /toolchain/binutils/binutils-2.25/bfd/ |
| coff-rs6000.c | 523 defined by shifts-and-ands, which are equivalent on all
627 defined by shifts-and-ands, which are equivalent on all
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-tbl.h | [all...] |
| i386-dis.c | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| AArch64InstrInfo.td | 183 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb2-instructions.s | 120 ands r3, r12, #0xf
125 @ CHECK: ands r3, r12, #15 @ encoding: [0x1c,0xf0,0x0f,0x03]
135 ands r2, r1, r7, lsl #1
136 ands.w r4, r5, r2, lsr #20
141 @ CHECK: ands.w r2, r1, r7, lsl #1 @ encoding: [0x11,0xea,0x47,0x02]
142 @ CHECK: ands.w r4, r5, r2, lsr #20 @ encoding: [0x15,0xea,0x12,0x54]
[all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_arm.S | 652 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
672 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
691 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
713 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
[all...] |
| /external/vixl/src/aarch32/ |
| disasm-aarch32.cc | 1219 void Disassembler::ands(Condition cond, function in class:vixl::aarch32::Disassembler
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| thumb2.txt | 105 # CHECK: ands r3, r12, #15
118 # CHECK: ands.w r2, r1, r7, lsl #1
119 # CHECK: ands.w r4, r5, r2, lsr #20
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| thumb2.txt | 103 # CHECK: ands r3, r12, #15
116 # CHECK: ands.w r2, r1, r7, lsl #1
117 # CHECK: ands.w r4, r5, r2, lsr #20
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/vixl/test/aarch64/ |
| test-trace-aarch64.cc | 65 __ ands(w5, w6, w7);
66 __ ands(x8, x9, x10);
[all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm64.cc | [all...] |
| /external/antlr/antlr-3.4/runtime/C/src/ |
| antlr3collections.c | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.h | [all...] |
| macro-assembler-arm64.h | 177 inline void Ands(const Register& rd,
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | 647 void ands(const Register& rd, const Register& rn, const Operand& operand);
[all...] |
| macro-assembler-aarch64.h | 615 void Ands(const Register& rd, const Register& rn, const Operand& operand);
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/gen/ |
| 386.rules | 628 // Fold extensions and ANDs together.
[all...] |
| ARM.rules | 527 // fold extensions and ANDs together
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/gen/ |
| 386.rules | 628 // Fold extensions and ANDs together.
[all...] |
| ARM.rules | 527 // fold extensions and ANDs together
[all...] |
