| /art/runtime/interpreter/mterp/arm64/ |
| op_cmpl_double.S | 1 %include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"lt"}
|
| op_cmpl_float.S | 1 %include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"}
|
| op_div_double_2addr.S | 1 %include "arm64/binopWide2addr.S" {"instr":"fdiv d0, d0, d1", "r0":"d0", "r1":"d1"}
|
| op_double_to_float.S | 1 %include "arm64/funopNarrower.S" {"instr":"fcvt s0, d0", "srcreg":"d0", "tgtreg":"s0"}
|
| op_double_to_int.S | 1 %include "arm64/funopNarrower.S" {"instr":"fcvtzs w0, d0", "srcreg":"d0", "tgtreg":"w0"}
|
| op_double_to_long.S | 1 %include "arm64/funopWide.S" {"instr":"fcvtzs x0, d0", "srcreg":"d0", "tgtreg":"x0"}
|
| op_float_to_double.S | 1 %include "arm64/funopWider.S" {"instr":"fcvt d0, s0", "srcreg":"s0", "tgtreg":"d0"}
|
| op_float_to_int.S | 1 %include "arm64/funopNarrow.S" {"instr":"fcvtzs w0, s0", "srcreg":"s0", "tgtreg":"w0"}
|
| op_float_to_long.S | 1 %include "arm64/funopWider.S" {"instr":"fcvtzs x0, s0", "srcreg":"s0", "tgtreg":"x0"}
|
| op_int_to_double.S | 1 %include "arm64/funopWider.S" {"instr":"scvtf d0, w0", "srcreg":"w0", "tgtreg":"d0"}
|
| op_int_to_float.S | 1 %include "arm64/funopNarrow.S" {"instr":"scvtf s0, w0", "srcreg":"w0", "tgtreg":"s0"}
|
| op_long_to_double.S | 1 %include "arm64/funopWide.S" {"instr":"scvtf d0, x0", "srcreg":"x0", "tgtreg":"d0"}
|
| op_long_to_float.S | 1 %include "arm64/funopNarrower.S" {"instr":"scvtf s0, x0", "srcreg":"x0", "tgtreg":"s0"}
|
| op_mul_double_2addr.S | 1 %include "arm64/binopWide2addr.S" {"instr":"fmul d0, d0, d1", "r0":"d0", "r1":"d1"}
|
| op_shl_int_lit8.S | 1 %include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"lsl w0, w0, w1"}
|
| op_shr_int_lit8.S | 1 %include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"asr w0, w0, w1"}
|
| op_sub_double_2addr.S | 1 %include "arm64/binopWide2addr.S" {"instr":"fsub d0, d0, d1", "r0":"d0", "r1":"d1"}
|
| op_ushr_int_lit8.S | 1 %include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"lsr w0, w0, w1"}
|
| /art/test/626-checker-arm64-scratch-register/ |
| info.txt | 1 Regression test checking that the ARM64 scratch register pool is not
|
| /art/test/658-fp-read-barrier/ |
| info.txt | 1 Regression test for the read barrier implementation in ARM64,
|
| /device/google/marlin/camera/mm-image-codec/ |
| Android.mk | 1 ifeq ($(TARGET_ARCH),$(filter $(TARGET_ARCH),arm arm64))
|
| /device/huawei/angler/camera/mm-image-codec/ |
| Android.mk | 1 ifeq ($(TARGET_ARCH),$(filter $(TARGET_ARCH),arm arm64))
|
| /device/lge/bullhead/camera/mm-image-codec/ |
| Android.mk | 1 ifeq ($(TARGET_ARCH),$(filter $(TARGET_ARCH),arm arm64))
|
| /external/clang/test/Driver/ |
| arm64-as.s | 1 // Make sure the arm64 default on cyclone when compiling for apple.
2 // RUN: %clang -target arm64-apple-ios -arch arm64 -### -c %s 2>&1 | FileCheck -check-prefix=TARGET %s
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/arm64/ |
| prog.go | 5 package arm64 package
10 "cmd/internal/obj/arm64"
27 var progtable = [arm64.ALAST & obj.AMask]gc.ProgInfo{
41 arm64.AHINT & obj.AMask: {Flags: gc.OK},
44 arm64.AADD & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
45 arm64.ASUB & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
46 arm64.ANEG & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, // why RegRead? revisit once the old backend gone
47 arm64.AAND & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
48 arm64.AORR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
49 arm64.AEOR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}
[all...] |
