| /external/llvm/test/TableGen/ |
| list-element-bitref.td | 10 def c0 : C<[0b0101, 0b1010]>;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64SystemOperands.td | 97 def : DC<"CVAC", 0b01, 0b011, 0b0111, 0b1010, 0b001>;
98 def : DC<"CSW", 0b01, 0b000, 0b0111, 0b1010, 0b010>;
376 def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>;
384 def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>;
397 def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>;
418 def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;
473 def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>;
489 def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>;
505 def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>;
521 def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrVFP.td | 464 def VMOVRS : AVConv2I<0b11100001, 0b1010,
485 def VMOVSR : AVConv4I<0b11100000, 0b1010,
529 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
578 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
652 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
670 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
725 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
743 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
764 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
778 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
[all...] |
| ARMInstrNEON.td | 226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
259 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
740 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
752 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
778 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
789 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
[all...] |
| ARMInstrThumb.td | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSystemInst.td | 26 let Inst{31-28} = 0b1010;
44 let Inst{31-28} = 0b1010;
98 let IClass = 0b1010;
|
| HexagonInstrEnc.td | 317 class V6_vL32b_nt_tmp_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1010>;
336 class V6_vL32b_nt_tmp_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1010>;
456 class V6_vS32b_nt_new_pred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b1010>;
473 class V6_vS32b_nt_new_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b1010>;
495 class V6_vL32b_nt_tmp_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1010>;
514 class V6_vL32b_nt_tmp_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1010>;
643 class V6_vS32b_nt_new_pred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b1010>;
660 class V6_vS32b_nt_new_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b1010>;
[all...] |
| HexagonInstrInfo.td | [all...] |
| HexagonInstrInfoV4.td | 422 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
480 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
549 let Inst{27-24} = 0b1010;
702 let IClass = 0b1010;
738 let IClass = 0b1010;
776 let IClass = 0b1010;
834 let IClass = 0b1010;
[all...] |
| HexagonInstrInfoV3.td | 239 let Inst{27-24} = 0b1010;
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| programmer-friendly.s | 22 // e.g. NzCv for #0xa (0b1010).
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrVFP.td | [all...] |
| ARMInstrNEON.td | 675 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
712 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
720 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
[all...] |
| ARMInstrThumb.td | 326 let Inst{9-6} = 0b1010;
[all...] |
| /external/clang/test/Lexer/ |
| cxx1y_digit_separators.cpp | 18 int e = 0'b1010; // expected-error {{digit 'b' in octal constant}}
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrAliases.td | 273 defm : int_cond_alias<"g", 0b1010>;
304 defm : fp_cond_alias<"ue", 0b1010>;
327 defm : cp_cond_alias<"03", 0b1010>;
|
| /prebuilts/go/darwin-x86/src/math/big/ |
| intconv_test.go | 359 {"0b1010", "%v", "10", 0},
|
| floatconv_test.go | 94 {"0b1010", 10},
|
| /prebuilts/go/linux-x86/src/math/big/ |
| intconv_test.go | 359 {"0b1010", "%v", "10", 0},
|
| floatconv_test.go | 94 {"0b1010", 10},
|
| /external/llvm/lib/Target/Mips/ |
| MicroMips32r6InstrFormats.td | 188 let Inst{15-12} = 0b1010;
450 let Inst{15-12} = 0b1010;
|
| MipsMSAInstrInfo.td | [all...] |
| MicroMips32r6InstrInfo.td | 229 class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-thumbv7.txt | 278 # VLD1 multi-element, type=0b1010 align=0b11
|
| /external/clang/lib/Lex/ |
| LiteralSupport.cpp | 777 /// number (like '04') or a hex number ('0x123a') a binary number ('0b1010') or
[all...] |
