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  /external/valgrind/none/tests/arm/
v6intThumb.c     [all...]
  /external/vixl/src/aarch64/
constants-aarch64.h 540 BICS = ANDS | NOT
584 BICS_w = LogicalShiftedFixed | BICS,
585 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
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macro-assembler-aarch64.cc 720 void MacroAssembler::Bics(const Register& rd,
724 LogicalMacro(rd, rn, operand, BICS);
804 case BICS:
823 case BICS:
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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
thumb32.d 143 0[0-9a-f]+ <[^>]+> 4380 bics r0, r0
144 0[0-9a-f]+ <[^>]+> 4385 bics r5, r0
145 0[0-9a-f]+ <[^>]+> 43a8 bics r0, r5
146 0[0-9a-f]+ <[^>]+> 43a8 bics r0, r5
147 0[0-9a-f]+ <[^>]+> ea35 0000 bics\.w r0, r5, r0
153 0[0-9a-f]+ <[^>]+> ea30 0000 bics\.w r0, r0, r0
    [all...]
  /external/v8/src/arm64/
macro-assembler-arm64-inl.h 80 void MacroAssembler::Bics(const Register& rd,
85 LogicalMacro(rd, rn, operand, BICS);
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  /bionic/libc/arch-arm/cortex-a9/bionic/
strcmp.S 422 bics r3, r3, #0xff000000
  /external/vixl/src/aarch32/
assembler-aarch32.h 2051 void bics(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
2054 void bics(Condition cond, Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
2057 void bics(EncodingSize size, function in class:vixl::aarch32::Assembler
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  /external/llvm/test/MC/Disassembler/ARM/
thumb1.txt 83 # BICS
85 # CHECK: bics r1, r6
  /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
thumb1.txt 79 # BICS
81 # CHECK: bics r1, r6
  /external/vixl/test/aarch32/
test-assembler-cond-rd-rn-operand-const-a32.cc 59 M(bics) \
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test-assembler-cond-rd-rn-operand-const-t32.cc 59 M(bics) \
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test-assembler-cond-rd-rn-operand-rm-a32.cc 59 M(bics) \
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test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc 59 M(bics) \
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test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc 59 M(bics) \
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test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc 59 M(bics) \
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test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc 59 M(bics) \
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test-assembler-cond-rd-rn-operand-rm-t32.cc 59 M(bics) \
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test-simulator-cond-rd-rn-operand-const-a32.cc 125 M(Bics) \
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test-simulator-cond-rd-rn-operand-const-t32.cc 125 M(Bics) \
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test-simulator-cond-rd-rn-operand-rm-a32.cc 125 M(Bics) \
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test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc 125 M(Bics) \
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test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc 125 M(Bics) \
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test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc 125 M(Bics) \
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test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc 125 M(Bics) \
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test-simulator-cond-rd-rn-operand-rm-t32.cc 125 M(Bics) \
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