| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| meminit.c | 501 uint8_t speed = mrc_params->ddr_speed & (BIT1|BIT0); // For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333
558 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
578 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
579 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
588 isbM32m(DDRPHY, (B0VREFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x03<<2)|(0x0<<1)|(0x0<<0)), ((BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|BIT1|BIT0)); // Internal Vref Code, Enable#, Ext_or_Int (1=Ext)
589 isbM32m(DDRPHY, (B1VREFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x03<<2)|(0x0<<1)|(0x0<<0)), ((BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|BIT1|BIT0)); // Internal Vref Code, Enable#, Ext_or_Int (1=Ext)
597 isbM32m(DDRPHY, (CMDCFGREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), 0, (BIT1|BIT0));
600 isbM32m(DDRPHY, (CMDRCOMPODT + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x03<<5)|(0x03<<0)), ((BIT9|BIT8|BIT7|BIT6|BIT5)|(BIT4|BIT3|BIT2|BIT1|BIT0)));
603 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
604 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSER (…)
[all...] |
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeHw.h | 62 #define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error
130 #define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO)
137 #define MPTCTRL_PME_EN BIT1 // Enable external PME signals
159 #define PHYSTS_JABBER BIT1 // Jabber condition detected
220 #define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P)
235 #define TXCFG_TX_ON BIT1 // Start the transmitter
265 #define MII_ACC_MII_WRITE BIT1
|
| /external/vulkan-validation-layers/include/vulkan/ |
| vulkan.hpp | 490 inline FramebufferCreateFlags operator|( FramebufferCreateFlagBits bit0, FramebufferCreateFlagBits bit1 )
492 return FramebufferCreateFlags( bit0 ) | bit1;
501 inline QueryPoolCreateFlags operator|( QueryPoolCreateFlagBits bit0, QueryPoolCreateFlagBits bit1 )
503 return QueryPoolCreateFlags( bit0 ) | bit1;
512 inline RenderPassCreateFlags operator|( RenderPassCreateFlagBits bit0, RenderPassCreateFlagBits bit1 )
514 return RenderPassCreateFlags( bit0 ) | bit1;
523 inline SamplerCreateFlags operator|( SamplerCreateFlagBits bit0, SamplerCreateFlagBits bit1 )
525 return SamplerCreateFlags( bit0 ) | bit1;
534 inline PipelineLayoutCreateFlags operator|( PipelineLayoutCreateFlagBits bit0, PipelineLayoutCreateFlagBits bit1 )
536 return PipelineLayoutCreateFlags( bit0 ) | bit1;
[all...] |
| /cts/tests/tests/widget/res/values/ |
| styles.xml | 125 <item name="testFlags">bit1</item>
137 <item name="testFlags">bit1|bit2</item>
141 <item name="testFlags">bit1|bit2|bit31</item>
|
| /external/libutf/ |
| rune.c | 21 Bit1 = 7,
28 T1 = ((1<<(Bit1+1))-1) ^ 0xFF, /* 0000 0000 */
35 Rune1 = (1<<(Bit1+0*Bitx))-1, /* 0000 0000 0111 1111 */
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 154 #define CLEARLOADMODE ~(BIT2 | BIT1)
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/ |
| XPressRich3.h | 48 #define PCIE_BAR_WIN_SUPPORT_IO32 BIT1
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
| AhciMode.h | 25 #define EFI_AHCI_GHC_IE BIT1
99 #define EFI_AHCI_PORT_IS_PSS BIT1
122 #define EFI_AHCI_PORT_CMD_SUD BIT1
164 #define EFI_AHCI_PORT_SERR_RCE BIT1
|
| IdeMode.h | 66 #define BMIS_ERROR BIT1
119 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 154 #define CLEARLOADMODE ~(BIT2 | BIT1)
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| VirtioBlk.h | 51 #define VIRTIO_BLK_F_SIZE_MAX BIT1
|
| /device/linaro/bootloader/edk2/OvmfPkg/Library/ResetSystemLib/ |
| ResetSystemLib.c | 50 IoWrite8 (0xCF9, BIT2 | BIT1); // 1st choice: PIIX3 RCR, RCPU|SRST
|
| /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/ |
| ArchDebugSupport.c | 43 if (((PcdGet32 (PcdExceptionsIgnoredByDebugger) & ~(BIT1 | BIT3)) & (1 << Index)) != 0) {
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 115 #define BIT1 0x00000002
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/NorFlashDxe/ |
| NorFlashDxe.h | 62 #define P30_SR_BIT_BLOCK_LOCKED (BIT1 << 16 | BIT1)
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/ |
| UsbMass.h | 46 #define USB_IS_BULK_ENDPOINT(Attribute) (((Attribute) & (BIT0 | BIT1)) == USB_ENDPOINT_BULK)
47 #define USB_IS_INTERRUPT_ENDPOINT(Attribute) (((Attribute) & (BIT0 | BIT1)) == USB_ENDPOINT_INTERRUPT)
|
| /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/ |
| PeCoffExtraActionLib.c | 36 return (BOOLEAN) (((Dr7 >> (RegisterIndex * 2)) & (BIT0 | BIT1)) == (BIT0 | BIT1));
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/ |
| IgdOpRegion.h | 72 #define HD_MBOX2 BIT1
95 #define BLC_ENABLE BIT1
|
| VlvPlatformInit.c | 100 PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));
185 PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 | BIT0));
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| reloc-insn.s | 138 orr x0,x0,bit1
206 .set bit1,0xf000000000000000
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
| XhciReg.h | 143 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
160 #define XHC_CRCR_CS BIT1 // Command Stop
167 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
184 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
194 #define XHC_IMAN_IE BIT1 // Interrupt Enable
|
| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| Acpi51.h | 197 #define EFI_ACPI_5_1_8042 BIT1
208 #define EFI_ACPI_5_1_ARM_PSCI_USE_HVC BIT1
215 #define EFI_ACPI_5_1_WBINVD_FLUSH BIT1
264 #define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F BIT1
520 #define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL BIT1
[all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/ |
| MMCSDTransfer.c | 824 if ((CardData->OCRRegister.AccessMode & BIT1) == BIT1) {
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| PlatformInfo.h | 347 TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)
349 TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge
350 TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530Dma.h | 110 #define DMA4_CSR_DROP BIT1
|
