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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
addsub.s 1 /* addsub.s Test file for AArch64 add-subtract instructions.
57 // normal add/adds/sub/subs
119 // normal add/adds/sub/subs
173 * Add-subtract (extended register)
176 .irp op, ADD, ADDS, SUB, SUBS
198 * Add-subtract (shift register)
201 .irp op, ADD, ADDS, SUB, SUBS
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
sp-pc-usage-t.s 19 add sp,sp,#0 label
23 add sp,sp,r0 label
24 add sp,sp,r0,lsl #1 label
43 @ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction.
45 add r0, sp, r0 label
47 add r0, sp, r0, lsl #1 label
62 @ ADD (sp plus immediate).
64 add sp, #4 label
65 add r0, sp, #4 label
70 add sp, sp, # label
76 add sp, r0 label
77 add r0, sp, r0 label
78 add r0, sp, r0, lsl #1 label
83 add sp, sp, r0 label
84 add sp, sp, r0, lsl #1 label
88 add sp, sp, sp label
112 add r0, pc, #4 label
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/epiphany/
regression.s 39 add r63,r63,r\num
157 /*2 REG ADD/SUB PROCESSING */
159 ADDLAB: ADD R63,R2,#3; //2+3=5
193 /*3-REGISTER ADD/SUB */
195 ADD3LAB: ADD R63,R2,R3 ; //3+2=5
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/
list-insns.s 51 ADD $12,$223,$1
52 ADD $122,$203,255
  /frameworks/support/v7/recyclerview/jvm-tests/src/android/support/v7/widget/
OpReorderTest.java 19 import static android.support.v7.widget.AdapterHelper.UpdateOp.ADD;
62 mRecycledOps.add(op);
212 orderedRandom(MOVE, ADD);
257 case ADD:
259 add(s, nextInt(random, 50)); method
297 UpdateOp add(int start, int count) { method in class:OpReorderTest
299 return record(new UpdateOp(ADD, start, count, null));
307 mUpdateOps.add(op);
314 items.add(Item.create());
318 clones.add(Item.clone(items.get(i)))
    [all...]
  /external/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 102 // normally expanded to the sequence SRA + SRL + ADD + SRA.
111 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info,
376 { ISD::ADD, MVT::v8i32, 4 },
378 { ISD::ADD, MVT::v4i64, 4 },
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X86SelectionDAGInfo.cpp 184 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
270 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
273 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeTypesGeneric.cpp 182 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
244 Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx);
247 Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
279 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
445 Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx);
447 Idx = DAG.getNode(ISD::ADD, dl,
497 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
LegalizeTypesGeneric.cpp 137 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
192 Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx);
195 Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
223 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
363 Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx);
365 Idx = DAG.getNode(ISD::ADD, dl,
413 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
  /external/mesa3d/src/mesa/swrast/
s_triangle.c 335 #define ADD \
433 SPAN_NEAREST(NEAREST_RGB;ADD,3);
452 SPAN_NEAREST(NEAREST_RGBA;ADD,4);
482 SPAN_LINEAR(LINEAR_RGB;ADD,3);
501 SPAN_LINEAR(LINEAR_RGBA;ADD,4);
705 SPAN_NEAREST(NEAREST_RGB;ADD,3);
724 SPAN_NEAREST(NEAREST_RGBA;ADD,4);
752 SPAN_LINEAR(LINEAR_RGB;ADD,3);
771 SPAN_LINEAR(LINEAR_RGBA;ADD,4);
923 * texturing. We add the specular color to the primary color
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUISelLowering.cpp 214 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
250 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
271 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
  /external/valgrind/none/tests/mips64/
arithmetic_instruction.c 6 ADD=0, ADDI, ADDIU, ADDU,
24 for (op = ADD; op <= SUBU; op++) {
27 case ADD:
31 TEST1("add $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
  /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/
sad_inline.h 55 x7 = x7 ^ src1; /* only odd bytes need to add carry */
58 src1 = src1 + (x7 >> 7); /* add 0xFF to the negative byte, add back carry */
147 x10 = x10 + x4; /* add with high bytes */
148 x10 = x10 + (x10 << 16); /* add with lower half word */
183 add sad, sad, tmp ;
201 ADD src1, src1, x7, asr #7; /* add 0xFF to the negative byte, add back carry */
216 EOR x7, x7, src1; /* only odd bytes need to add carry *
    [all...]
  /developers/samples/android/ui/DrawableTinting/Application/src/test/
SampleTests.java 77 //Try to add a message to add context to your assertions. These messages will be shown if
91 assertEquals("Add", (String) mBlendMode.getSelectedItem());
97 assertEquals(PorterDuff.Mode.ADD, colorFilter.getMode());
  /development/ndk/platforms/android-21/include/arpa/
nameser_compat.h 181 #define ADD ns_uop_add
  /device/linaro/bootloader/edk2/StdLib/Include/arpa/
nameser_compat.h 179 #define ADD ns_uop_add
  /external/dexmaker/dexmaker-tests/src/androidTest/java/com/android/dx/examples/
FibonacciMaker.java 60 code.op(BinaryOp.ADD, result, c, d);
  /external/llvm/lib/Target/Mips/
MipsISelLowering.h 305 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
319 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
338 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
346 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
356 // (add %hi(sym), %lo(sym))
362 return DAG.getNode(ISD::ADD, DL, Ty,
370 // (add $gp, %gp_rel(sym))
376 return DAG.getNode(ISD::ADD, DL, Ty,
534 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_opcode_tmp.h 51 OP12(ADD)
  /external/proguard/src/proguard/evaluation/value/
SpecificLongValue.java 60 public LongValue add(LongValue other) method in class:SpecificLongValue
62 return other.add(this);
148 public LongValue add(SpecificLongValue other) method in class:SpecificLongValue
150 return new CompositeLongValue(this, CompositeLongValue.ADD, other);
  /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
ISDOpcodes.h 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
206 // results. The first result is the normal add or sub result, the second
212 // the add or sub, and the third is the input carry flag. These nodes
213 // produce two results; the normal result of the add or sub, and the output
215 // to them to be chained together for add and sub of arbitrarily large
220 // These nodes take two operands: the normal LHS and RHS to the add. They
221 // produce two results: the normal result of the add, and a boolean that
225 // These nodes are generated from the llvm.[su]add.with.overflow intrinsics.
347 // integer shift operations, just like ADD/SUB_PARTS. The operation
654 /// PRE_DEC the value of the base pointer add / subtract the offset
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  /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
BlackfinISelDAGToDAG.cpp 105 if (Addr.getOpcode() == ISD::ADD) {
  /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/
omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.s 442 ADD pThresholds, #4
452 ADD pQ0, pQ0, #4
461 ADD pThresholds, pThresholds, #4
547 ADD pQ0, pQ0, srcdstStep, LSL #2
  /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/
armVCM4P10_DeblockingChroma_unsafe_s.s 202 ADD pThresholds, pThresholds, #4
armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s 88 ADD Temp, pSrc, srcStep, LSL #2

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