| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/ |
| rewritePPC64.go | 10 switch v.Op {
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/ |
| rewritePPC64.go | 10 switch v.Op {
[all...] |
| /cts/tests/tests/graphics/src/android/graphics/cts/ |
| RegionIteratorTest.java | 67 region.op(rect, Region.Op.UNION);
94 region.op(rect, Region.Op.DIFFERENCE);
116 region.op(rect, Region.Op.INTERSECT);
133 region.op(rect, Region.Op.REVERSE_DIFFERENCE);
155 region.op(rect, Region.Op.XOR)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFixIrreducibleControlFlow.cpp | 251 for (auto &Op : Term.explicit_uses())
252 if (Op.isMBB() && Indices.count(Op.getMBB()))
253 Op.setMBB(Map[Op.getMBB()]);
|
| WebAssemblyRegStackify.cpp | 434 static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op,
454 Op.setReg(NewReg);
462 LIS.getInstructionIndex(*Op.getParent()).getRegSlot(),
477 unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB,
482 DEBUG(dbgs() << " - for use in "; Op.getParent()->dump());
486 Op.setReg(NewReg);
537 unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB,
555 Op.setReg(TeeReg);
601 MachineOperand &Op = *Range.begin();
608 return Op;
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.h | 42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
44 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
49 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
50 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS);
|
| X86IntelInstPrinter.h | 37 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
38 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O);
44 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O);
|
| /external/spirv-llvm/lib/SPIRV/ |
| OCL21ToSPIRV.cpp | 70 // __spirv{N}Op{ConvertOpName}(src, dummy)
73 void visitCallConvert(CallInst *CI, StringRef MangledName, Op OC);
77 /// y = __spirv{N}Op{Decorate}(x, type, value, dummy)
90 void transBuiltin(CallInst *CI, Op OC);
163 Op OC = OpNop;
180 StringRef MangledName, Op OC) {
223 OCL21ToSPIRV::transBuiltin(CallInst* CI, Op OC) {
|
| SPIRVRegularizeLLVM.cpp | 80 /// Assuming F is a SPIR-V builtin function with op code \param OC.
81 void lowerFuncPtr(Function *F, Op OC);
173 void SPIRVRegularizeLLVM::lowerFuncPtr(Function* F, Op OC) {
194 std::vector<std::pair<Function *, Op>> Work;
|
| /external/swiftshader/third_party/LLVM/lib/Transforms/Utils/ |
| ValueMapper.cpp | 65 Value *OP = MD->getOperand(i);
66 if (OP == 0 || MapValue(OP, VM, Flags, TypeMapper) == OP) continue;
72 Value *Op = MD->getOperand(i);
73 Elts.push_back(Op ? MapValue(Op, VM, Flags, TypeMapper) : 0);
108 Value *Op = C->getOperand(OpNo);
109 Mapped = MapValue(Op, VM, Flags, TypeMapper);
163 for (User::op_iterator op = I->op_begin(), E = I->op_end(); op != E; ++op)
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 330 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
394 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
4814 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); local
4821 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); local
6507 int op = (Operands[2]->isImm()) ? 2 : 3; local
[all...] |
| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| SPIRVInstruction.h | 67 bool isSpecConstantOpAllowedOp(Op OC);
106 SPIRVInstruction(unsigned TheWordCount, Op TheOC, SPIRVType *TheType,
109 SPIRVInstruction(unsigned TheWordCount, Op TheOC,
113 SPIRVInstruction(unsigned TheWordCount, Op TheOC, SPIRVId TheId,
116 SPIRVInstruction(unsigned TheWordCount, Op TheOC,
119 SPIRVInstruction(unsigned TheWordCount, Op TheOC, SPIRVType *TheType,
122 SPIRVInstruction(Op TheOC = OpNop):SPIRVValue(TheOC), BB(NULL){}
182 static SPIRVInstTemplateBase *create(Op TheOC){
189 static SPIRVInstTemplateBase *create(Op TheOC, SPIRVType *TheType,
197 static SPIRVInstTemplateBase *create(Op TheOC, SPIRVType *TheType
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 308 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
709 auto Op = make_unique<PPCOperand>(Token);
710 Op->Tok.Data = Str.data();
711 Op->Tok.Length = Str.size();
712 Op->StartLoc = S;
713 Op->EndLoc = S;
714 Op->IsPPC64 = IsPPC64;
715 return Op;
726 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
727 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1)
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/gc/ |
| inl.go | 88 if fn.Op != ODCLFUNC {
197 switch n.Op {
237 *reason = "non-leaf op " + n.Op.String()
252 *reason = "unhandled op " + n.Op.String()
259 switch n.Op {
289 switch n.Op {
322 n.Op = OBLOCK
345 if n.Op != OINLCALL || n.Rlist.Len() == 0
[all...] |
| order.go | 15 // Rewrite x op= y into x = x op y.
101 switch n.Op {
126 switch n.Op {
167 Fatalf("ordersafeexpr %v", n.Op)
179 return islvalue(n) && (n.Op != ONAME || n.Class == PEXTERN || n.IsAutoTmp())
303 switch n.Op {
350 // n->op is OCALLMETH/OCALLFUNC/OCALLINTER or a builtin like OCOPY.
356 if n.Op == OCALLFUNC {
369 for (*xp).Op == OCONVNOP && !(*xp).Type.IsPtr()
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/s390x/ |
| ssa.go | 24 if flive && v.Op == ssa.OpS390XMOVDconst {
132 // dest := dest(To) op src(From)
135 func opregreg(op obj.As, dest, src int16) *obj.Prog {
136 p := gc.Prog(op)
145 // dest := src(From) op off
148 func opregregimm(op obj.As, dest, src int16, off int64) *obj.Prog {
149 p := gc.Prog(op)
160 switch v.Op {
170 p := opregreg(v.Op.Asm(), r, r2)
182 p := opregreg(v.Op.Asm(), r, r2
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/gc/ |
| inl.go | 88 if fn.Op != ODCLFUNC {
197 switch n.Op {
237 *reason = "non-leaf op " + n.Op.String()
252 *reason = "unhandled op " + n.Op.String()
259 switch n.Op {
289 switch n.Op {
322 n.Op = OBLOCK
345 if n.Op != OINLCALL || n.Rlist.Len() == 0
[all...] |
| order.go | 15 // Rewrite x op= y into x = x op y.
101 switch n.Op {
126 switch n.Op {
167 Fatalf("ordersafeexpr %v", n.Op)
179 return islvalue(n) && (n.Op != ONAME || n.Class == PEXTERN || n.IsAutoTmp())
303 switch n.Op {
350 // n->op is OCALLMETH/OCALLFUNC/OCALLINTER or a builtin like OCOPY.
356 if n.Op == OCALLFUNC {
369 for (*xp).Op == OCONVNOP && !(*xp).Type.IsPtr()
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/s390x/ |
| ssa.go | 24 if flive && v.Op == ssa.OpS390XMOVDconst {
132 // dest := dest(To) op src(From)
135 func opregreg(op obj.As, dest, src int16) *obj.Prog {
136 p := gc.Prog(op)
145 // dest := src(From) op off
148 func opregregimm(op obj.As, dest, src int16, off int64) *obj.Prog {
149 p := gc.Prog(op)
160 switch v.Op {
170 p := opregreg(v.Op.Asm(), r, r2)
182 p := opregreg(v.Op.Asm(), r, r2
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135 return BitConvertToInteger(Op);
192 SDValue Op = GetSoftenedFloat(N->getOperand(0));
193 return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
237 SDValue Op = GetSoftenedFloat(N->getOperand(0));
244 NVT, Op, false, SDLoc(N)).first;
300 SDValue Op = GetSoftenedFloat(N->getOperand(0));
307 NVT, Op, false, SDLoc(N)).first;
325 SDValue Op = GetSoftenedFloat(N->getOperand(0));
332 NVT, Op, false, SDLoc(N)).first
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SITypeRewriter.cpp | 148 if (BitCastInst *Op = dyn_cast<BitCastInst>(I.getOperand(0))) {
149 if (Op->getSrcTy() == v4i32) {
150 I.replaceAllUsesWith(Op->getOperand(0));
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 113 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
114 return BitConvertToInteger(Op);
147 SDValue Op = GetSoftenedFloat(N->getOperand(0));
148 return DAG.getNode(ISD::AND, N->getDebugLoc(), NVT, Op, Mask);
165 SDValue Op = GetSoftenedFloat(N->getOperand(0));
171 NVT, &Op, 1, false, N->getDebugLoc());
218 SDValue Op = GetSoftenedFloat(N->getOperand(0));
224 NVT, &Op, 1, false, N->getDebugLoc());
241 SDValue Op = GetSoftenedFloat(N->getOperand(0));
247 NVT, &Op, 1, false, N->getDebugLoc())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| InstCombineLoadStoreAlloca.cpp | 145 Value *Op = LI.getOperand(0);
150 getOrEnforceKnownAlignment(Op, TD->getPrefTypeAlignment(LI.getType()),TD);
162 if (isa<CastInst>(Op))
174 if (Value *AvailableVal = FindAvailableLoadedValue(Op, LI.getParent(), BBI,6))
178 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(Op)) {
187 Constant::getNullValue(Op->getType()), &LI);
194 if (isa<UndefValue>(Op) ||
195 (isa<ConstantPointerNull>(Op) && LI.getPointerAddressSpace() == 0)) {
200 Constant::getNullValue(Op->getType()), &LI);
205 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Op))
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| plan9x.go | 37 op := inst.Op.String()
39 switch inst.Op &^ 15 {
44 if inst.Op&^15 == LDR_EQ && reg == R15 && mem.Base == SP && mem.Sign == 0 && mem.Mode == AddrPostIndex {
45 return fmt.Sprintf("RET%s #%d", op[3:], mem.Offset)
52 switch inst.Op &^ 15 {
81 switch inst.Op &^ 15 {
117 switch inst.Op &^ 15 {
119 op = "MOVW" + op[3:
[all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| plan9x.go | 37 op := inst.Op.String()
39 switch inst.Op &^ 15 {
44 if inst.Op&^15 == LDR_EQ && reg == R15 && mem.Base == SP && mem.Sign == 0 && mem.Mode == AddrPostIndex {
45 return fmt.Sprintf("RET%s #%d", op[3:], mem.Offset)
52 switch inst.Op &^ 15 {
81 switch inst.Op &^ 15 {
117 switch inst.Op &^ 15 {
119 op = "MOVW" + op[3:
[all...] |
