| /external/cblas/src/ |
| cblas_sspr2.c | 16 char UL;
20 #define F77_UL &UL
37 if (Uplo == CblasLower) UL = 'L';
38 else if (Uplo == CblasUpper) UL = 'U';
47 F77_UL = C2F_CHAR(&UL);
55 if (Uplo == CblasLower) UL = 'U';
56 else if (Uplo == CblasUpper) UL = 'L';
65 F77_UL = C2F_CHAR(&UL);
|
| cblas_ssymv.c | 18 char UL;
22 #define F77_UL &UL
39 if (Uplo == CblasUpper) UL = 'U';
40 else if (Uplo == CblasLower) UL = 'L';
49 F77_UL = C2F_CHAR(&UL);
57 if (Uplo == CblasUpper) UL = 'L';
58 else if (Uplo == CblasLower) UL = 'U';
67 F77_UL = C2F_CHAR(&UL);
|
| cblas_ssyr.c | 15 char UL;
19 #define F77_UL &UL
35 if (Uplo == CblasLower) UL = 'L';
36 else if (Uplo == CblasUpper) UL = 'U';
45 F77_UL = C2F_CHAR(&UL);
53 if (Uplo == CblasLower) UL = 'U';
54 else if (Uplo == CblasUpper) UL = 'L';
63 F77_UL = C2F_CHAR(&UL);
|
| cblas_ssyr2.c | 17 char UL;
21 #define F77_UL &UL
39 if (Uplo == CblasLower) UL = 'L';
40 else if (Uplo == CblasUpper) UL = 'U';
49 F77_UL = C2F_CHAR(&UL);
58 if (Uplo == CblasLower) UL = 'U';
59 else if (Uplo == CblasUpper) UL = 'L';
68 F77_UL = C2F_CHAR(&UL);
|
| cblas_chemm.c | 18 char SD, UL;
23 #define F77_UL &UL
54 if( Uplo == CblasUpper) UL='U';
55 else if ( Uplo == CblasLower ) UL='L';
65 F77_UL = C2F_CHAR(&UL);
84 if( Uplo == CblasUpper) UL='L';
85 else if ( Uplo == CblasLower ) UL='U';
95 F77_UL = C2F_CHAR(&UL);
|
| cblas_cher.c | 16 char UL;
20 #define F77_UL &UL
40 if (Uplo == CblasLower) UL = 'L';
41 else if (Uplo == CblasUpper) UL = 'U';
50 F77_UL = C2F_CHAR(&UL);
58 if (Uplo == CblasUpper) UL = 'L';
59 else if (Uplo == CblasLower) UL = 'U';
68 F77_UL = C2F_CHAR(&UL);
|
| cblas_cher2k.c | 18 char UL, TR;
23 #define F77_UL &UL
48 if( Uplo == CblasUpper) UL='U';
49 else if ( Uplo == CblasLower ) UL='L';
70 F77_UL = C2F_CHAR(&UL);
79 if( Uplo == CblasUpper) UL='L';
80 else if ( Uplo == CblasLower ) UL='U';
99 F77_UL = C2F_CHAR(&UL);
|
| /external/compiler-rt/test/sanitizer_common/TestCases/ |
| strnlen.c | 7 assert(strnlen(s, 0) == 0UL);
8 assert(strnlen(s, 1) == 1UL);
|
| /external/syslinux/gpxe/src/drivers/bitbash/ |
| bitbash.c | 41 basher->op->write ( basher, bit_id, ( data ? -1UL : 0 ) );
51 * @c data will always be either 0 or -1UL. The idea is that the
56 return ( basher->op->read ( basher, bit_id ) ? -1UL : 0 );
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530Uart.h | 37 #define UART_LCR_DIV_EN_DISABLE (0UL << 7)
44 #define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5)
48 #define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0)
51 #define UART_MDR1_MODE_SELECT_DISABLE (7UL)
52 #define UART_MDR1_MODE_SELECT_UART_16X (0UL)
|
| /device/linaro/bootloader/arm-trusted-firmware/include/drivers/arm/ |
| gic_v3.h | 44 #define WAKER_CA (1UL << 2)
45 #define WAKER_PS (1UL << 1)
50 #define GICR_TYPER_LAST (1UL << 4)
53 #define ICC_SRE_EN (1UL << 3)
54 #define ICC_SRE_SRE (1UL << 0)
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530Uart.h | 37 #define UART_LCR_DIV_EN_DISABLE (0UL << 7)
44 #define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5)
48 #define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0)
51 #define UART_MDR1_MODE_SELECT_DISABLE (7UL)
52 #define UART_MDR1_MODE_SELECT_UART_16X (0UL)
|
| /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| core_cm4.h | 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
479 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
482 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask *
[all...] |
| core_cm7.h | 482 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
485 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
488 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
491 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
494 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
497 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
500 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
506 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
523 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
526 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask *
[all...] |
| core_cm3.h | 391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
415 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
423 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
440 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask *
[all...] |
| core_sc300.h | 391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
415 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
422 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
435 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask *
[all...] |
| /external/syslinux/core/lwip/src/netif/ppp/ |
| md5.c | 105 #define UL(x) x##UL
108 #define UL(x) x##UL
110 #define UL(x) x
229 FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
230 FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
231 FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
232 FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
233 FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 *
[all...] |
| /bionic/libc/kernel/uapi/rdma/hfi/ |
| hfi1_user.h | 26 #define HFI1_CAP_DMA_RTAIL (1UL << 0)
27 #define HFI1_CAP_SDMA (1UL << 1)
29 #define HFI1_CAP_SDMA_AHG (1UL << 2)
30 #define HFI1_CAP_EXTENDED_PSN (1UL << 3)
31 #define HFI1_CAP_HDRSUPP (1UL << 4)
32 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6)
34 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7)
35 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8)
36 #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9)
37 #define HFI1_CAP_TID_UNMAP (1UL << 10
[all...] |
| /external/kernel-headers/original/uapi/rdma/hfi/ |
| hfi1_user.h | 91 #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */
92 #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */
93 #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */
94 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */
95 #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */
96 /* 1UL << 5 unused */
97 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */
98 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/
99 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */
100 #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full *
[all...] |
| /external/ppp/pppd/ |
| md5.c | 97 #define UL(x) x##U
99 #define UL(x) x
214 FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
215 FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
216 FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
217 FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
218 FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
219 FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
220 FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
221 FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 *
[all...] |
| /external/strace/linux/ia64/ |
| arch_regs.c | 4 #define IA64_PSR_IS (1UL << 34)
|
| /external/syslinux/com32/include/bitsize64/ |
| stdint.h | 20 #define __UINT64_C(c) c ## UL
|
| /device/google/contexthub/firmware/os/platform/stm32/ |
| mpu.c | 44 #define MPU_BIT_XN (1UL << 28) /* no execute */
47 #define MPU_NA (0UL << 24) /* S: no access U: no access */
48 #define MPU_U_NA_S_RW (1UL << 24) /* S: RW U: no access */
49 #define MPU_U_RO_S_RW (2UL << 24) /* S: RW U: RO */
50 #define MPU_RW (3UL << 24) /* S: RW U: RW */
51 #define MPU_U_NA_S_RO (5UL << 24) /* S: RO U: no access */
52 #define MPU_U_RO_S_RO (6UL << 24) /* S: RO U: RO */
56 #define MPU_BIT_ENABLE 1UL
|
| /device/linaro/bootloader/edk2/StdLib/Include/Ipf/machine/ |
| int_const.h | 57 #define UINT64_C(c) c ## UL
62 #define UINTMAX_C(c) c ## UL
|
| /external/ImageMagick/MagickCore/ |
| magick-type.h | 47 #define MaxColormapSize 256UL
48 #define MaxMap 255UL
61 #define MaxColormapSize 65536UL
62 #define MaxMap 65535UL
75 #define MaxColormapSize 65536UL
76 #define MaxMap 65535UL
90 #define MaxColormapSize 65536UL
91 #define MaxMap 65535UL
|
