| /external/llvm/lib/CodeGen/ |
| XRayInstrumentation.cpp | 64 BuildMI(FirstMBB, FirstMI, FirstMI.getDebugLoc(),
76 auto MIB = BuildMI(MBB, T, T.getDebugLoc(),
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 56 MI = BuildMI(MBB, MI, dl,
61 BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode),
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCBranchSelector.cpp | 201 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
205 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
208 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
210 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
212 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
214 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
216 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
222 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| PPCTLSDynamicCall.cpp | 102 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0);
105 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
114 MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
118 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
120 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
|
| PPCFrameLowering.cpp | 351 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
355 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
360 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
364 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
369 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
373 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
377 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
850 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
853 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
860 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg)
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 10 // This file exposes a function named BuildMI, which is useful for dramatically
13 // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
178 /// BuildMI - Builder interface. Specify how to create the initial instruction
181 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
187 /// BuildMI - This version of the builder sets up the first operand as a
190 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
198 /// BuildMI - This version of the builder inserts the newly-built
202 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
212 /// BuildMI - This version of the builder inserts the newly-built
216 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ScheduleDAGEmit.cpp | 54 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
63 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsEmitGPRestore.cpp | 67 BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
80 BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.cpp | 97 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
108 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
115 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
128 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
133 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
138 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
143 BuildMI(MBB, I, DL,
147 BuildMI(MBB, I, DL,
270 BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
285 BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 53 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
63 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPUSH)))
65 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPOP)))
90 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
116 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| ARMFrameLowering.cpp | 216 BuildMI(MBB, std::next(Info.I), dl,
256 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
261 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
270 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
274 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
282 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
451 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
455 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
464 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
472 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 96 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::LO), DestReg)
98 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::HI), DestReg)
120 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi),
146 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi),
149 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi),
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.cpp | 75 BuildMI(MBB, I, DL, get(CopyLocalOpcode), DestReg)
173 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
180 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).addOperand(Cond[1]);
182 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS))
189 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
354 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
370 BuildMI(MBB, I, DL, get(XCore::STWFI))
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
147 BuildMI(MBB, II, dl, TII.get(NewOpcode))
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
177 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0)
[all...] |
| XCoreInstrInfo.cpp | 285 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
289 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
298 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
300 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
336 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
343 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
348 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
371 BuildMI(MBB, I, DL, get(XCore::STWFI))
393 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
434 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 159 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
173 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
197 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
199 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
219 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
221 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
252 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
253 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
255 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
256 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY))
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32),
134 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr)
138 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
160 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0)
164 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1)
168 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMFastISel.cpp | 283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
318 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
321 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
342 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
346 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 257 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r)
265 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17)
268 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18)
274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11)
276 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11)
279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11)
281 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR)
286 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18)
289 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17)
295 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), r
[all...] |
| MBlazeInstrInfo.cpp | 80 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
88 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg)
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
108 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
209 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
291 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 120 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
130 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
187 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
207 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
232 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
370 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
381 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
398 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
433 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
554 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(FirstOpc)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 129 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
134 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
147 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
149 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
152 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
186 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
198 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
|
| SparcFrameLowering.cpp | 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
163 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
168 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
176 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFRegisterInfo.cpp | 69 BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
87 BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
89 BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
|
