| /external/llvm/include/llvm/ADT/ |
| SparseSet.h | 201 /// @param Idx A valid index to find.
204 iterator findIndex(unsigned Idx) {
205 assert(Idx < Universe && "Key out of range");
207 for (unsigned i = Sparse[Idx], e = size(); i < e; i += Stride) {
210 if (Idx == FoundIdx)
250 unsigned Idx = ValIndexOf(Val);
251 iterator I = findIndex(Idx);
254 Sparse[Idx] = size();
|
| BitVector.h | 51 reference(BitVector &b, unsigned Idx) {
52 WordRef = &b.Bits[Idx / BITWORD_SIZE];
53 BitPos = Idx % BITWORD_SIZE;
225 BitVector &set(unsigned Idx) {
227 Bits[Idx / BITWORD_SIZE] |= BitWord(1) << (Idx % BITWORD_SIZE);
265 BitVector &reset(unsigned Idx) {
266 Bits[Idx / BITWORD_SIZE] &= ~(BitWord(1) << (Idx % BITWORD_SIZE));
306 BitVector &flip(unsigned Idx) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| SplitKit.h | 149 /// (re-)defined at Idx. Idx should be the 'def' slot for a normal kill/def,
153 bool isOriginalEndpoint(SlotIndex Idx) const;
260 /// Edit.get(RegAssign.lookup(Idx)) is the register that should be live at
261 /// Idx.
293 /// defValue - define a value in RegIdx from ParentVNI at Idx.
294 /// Idx does not have to be ParentVNI->def, but it must be contained within
298 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx);
359 void selectIntv(unsigned Idx);
361 /// enterIntvBefore - Enter the open interval before the instruction at Idx
[all...] |
| LiveDebugVariables.cpp | 127 /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo.
128 void insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo,
204 void addDef(SlotIndex Idx, const MachineOperand &LocMO) {
205 // Add a singular (Idx,Idx) -> Loc mapping.
206 LocMap::iterator I = locInts.find(Idx);
207 if (!I.valid() || I.start() != Idx)
208 I.insert(Idx, Idx.getNextSlot(), getLocationNo(LocMO));
218 /// @param Idx Starting point for the definition
[all...] |
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| Attributes.cpp | 244 /// returned. Attributes for the result are denoted with Idx = 0.
245 /// Function notes are denoted with idx = ~0.
246 Attributes AttrListPtr::getAttributes(unsigned Idx) const {
250 for (unsigned i = 0, e = Attrs.size(); i != e && Attrs[i].Index <= Idx; ++i)
251 if (Attrs[i].Index == Idx)
269 AttrListPtr AttrListPtr::addAttr(unsigned Idx, Attributes Attrs) const {
270 Attributes OldAttrs = getAttributes(Idx);
286 NewAttrList.push_back(AttributeWithIndex::get(Idx, Attrs));
291 for (; i != e && OldAttrList[i].Index < Idx; ++i)
295 if (i != e && OldAttrList[i].Index == Idx) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBlockRanges.cpp | 162 IndexType Idx = IndexType::First;
163 First = Idx;
168 Map.insert(std::make_pair(Idx, &In));
169 ++Idx;
171 Last = B.empty() ? IndexType::None : unsigned(Idx)-1;
175 MachineInstr *HexagonBlockRanges::InstrIndexMap::getInstr(IndexType Idx) const {
176 auto F = Map.find(Idx);
191 IndexType Idx) const {
192 assert (Idx != IndexType::None);
193 if (Idx == IndexType::Entry
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveDebugVariables.cpp | 132 /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo.
133 void insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo,
214 void addDef(SlotIndex Idx, const MachineOperand &LocMO) {
215 // Add a singular (Idx,Idx) -> Loc mapping.
216 LocMap::iterator I = locInts.find(Idx);
217 if (!I.valid() || I.start() != Idx)
218 I.insert(Idx, Idx.getNextSlot(), getLocationNo(LocMO));
228 /// @param Idx Starting point for the definition
[all...] |
| TargetSchedule.cpp | 64 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
65 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
70 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
71 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
72 ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
|
| LiveRangeEdit.cpp | 223 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
224 if (LI.Query(Idx).isKill())
230 if ((S.LaneMask & LaneMask) != 0 && S.Query(Idx).isKill())
240 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
248 DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
255 DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
259 DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
270 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
276 isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
290 LIS.removePhysRegDefAt(Reg, Idx);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64A57FPLoadBalancing.cpp | 147 void scanInstruction(MachineInstr *MI, unsigned Idx,
150 void maybeKillChain(MachineOperand &MO, unsigned Idx,
208 Chain(MachineInstr *MI, unsigned Idx, Color C)
210 StartInstIdx(Idx), LastInstIdx(Idx), KillInstIdx(0),
217 void add(MachineInstr *MI, unsigned Idx, Color C) {
219 LastInstIdx = Idx;
238 void setKill(MachineInstr *MI, unsigned Idx, bool Immutable) {
240 KillInstIdx = Idx;
346 unsigned Idx = 0
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| StraightLineStrengthReduce.cpp | 94 Candidate(Kind CT, const SCEV *B, ConstantInt *Idx, Value *S,
96 : CandidateKind(CT), Base(B), Index(Idx), Stride(S), Ins(I),
174 // A helper function that scales Idx with ElementSize before invoking
176 void allocateCandidatesAndFindBasisForGEP(const SCEV *B, ConstantInt *Idx,
179 // Adds the given form <CT, B, Idx, S> to Candidates, and finds its immediate
182 ConstantInt *Idx, Value *S,
301 Candidate::Kind CT, const SCEV *B, ConstantInt *Idx, Value *S,
303 Candidate C(CT, B, Idx, S, I);
367 ConstantInt *Idx = nullptr;
368 if (match(RHS, m_Mul(m_Value(S), m_ConstantInt(Idx)))) {
[all...] |
| ConstantHoisting.cpp | 119 unsigned Idx) const {
122 if (Idx != ~0U) {
123 Value *Opnd = Inst->getOperand(Idx);
136 if (Idx != ~0U && isa<PHINode>(Inst))
137 return cast<PHINode>(Inst)->getIncomingBlock(Idx)->getTerminator();
174 /// index Idx.
176 /// The operand at index Idx is not necessarily the constant integer itself. It
180 ConstCandMapType &ConstCandMap, Instruction *Inst, unsigned Idx,
186 Cost = TTI->getIntImmCost(IntrInst->getIntrinsicID(), Idx,
189 Cost = TTI->getIntImmCost(Inst->getOpcode(), Idx, ConstInt->getValue()
[all...] |
| /frameworks/compile/slang/tests/P_reduce_general_result/ |
| ScriptC_reduce_general_result.java.expect | 118 for (int Idx = 0; Idx < 7; ++Idx) {
119 result[Idx] = outArray[Idx] != 0;
195 for (int Idx = 0; Idx < 7; ++Idx) {
196 result[Idx] = new Byte2(outArray[2*Idx+0], outArray[2*Idx+1])
[all...] |
| /external/llvm/unittests/ADT/ |
| HashingTest.cpp | 177 for (unsigned Idx = 1, Size = all_one_c.size(); Idx < Size; ++Idx) {
178 hash_code code = hash_combine_range(&all_one_c[0], &all_one_c[0] + Idx);
180 I = code_to_size.insert(std::make_pair(code, Idx)).first;
181 EXPECT_EQ(Idx, I->second);
185 for (unsigned Idx = 1, Size = all_zero_c.size(); Idx < Size; ++Idx) {
186 hash_code code = hash_combine_range(&all_zero_c[0], &all_zero_c[0] + Idx);
[all...] |
| /external/clang/include/clang/Serialization/ |
| ASTDeserializationListener.h | 45 virtual void TypeRead(serialization::TypeIdx Idx, QualType T) { }
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 187 /// each Idx such that:
191 /// this->contains(Reg:Idx)
511 const TargetRegisterClass *B, unsigned Idx) const;
523 /// supports the sub-register index Idx.
525 /// If all registers in RC already have an Idx sub-register, return RC.
535 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
536 assert(Idx == 0 && "Target has no sub-registers");
574 /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
575 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
729 virtual const char *getRegPressureSetName(unsigned Idx) const = 0
[all...] |
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiAsmBackend.cpp | 108 unsigned Idx = (FullSize - 1 - i);
109 CurVal |= static_cast<uint64_t>(static_cast<uint8_t>(Data[Offset + Idx]))
119 unsigned Idx = (FullSize - 1 - i);
120 Data[Offset + Idx] = static_cast<uint8_t>((CurVal >> (i * 8)) & 0xff);
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZRegisterInfo.h | 41 const TargetRegisterClass *B, unsigned Idx) const;
|
| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/QemuFwCfgLib/ |
| QemuFwCfgLib.c | 319 UINTN Idx;
321 for (Idx = 0; Idx < Size; ++Idx) {
322 MmioWrite8 (mFwCfgDataAddress, ((UINT8 *)Buffer)[Idx]);
426 UINT32 Idx;
435 for (Idx = 0; Idx < Count; ++Idx) {
|
| /device/linaro/bootloader/edk2/OvmfPkg/Library/VirtioLib/ |
| VirtioLib.c | 66 sizeof *Ring->Avail.Idx +
73 sizeof *Ring->Used.Idx +
92 Ring->Avail.Idx = (volatile VOID *) RingPagesPtr;
93 RingPagesPtr += sizeof *Ring->Avail.Idx;
108 Ring->Used.Idx = (volatile VOID *) RingPagesPtr;
109 RingPagesPtr += sizeof *Ring->Used.Idx;
278 NextAvailIdx = *Ring->Avail.Idx;
286 *Ring->Avail.Idx = NextAvailIdx;
308 while (*Ring->Used.Idx != NextAvailIdx) {
|
| /external/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 47 DEBUG(for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
48 const RegisterBank &RegBank = getRegBank(Idx);
49 assert(Idx == RegBank.getID() &&
474 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
475 const MachineOperand &MO = MI.getOperand(Idx);
476 const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| LiveInterval.h | 396 const LiveRange *getLiveRangeContaining(SlotIndex Idx) const {
397 const_iterator I = FindLiveRangeContaining(Idx);
403 LiveRange *getLiveRangeContaining(SlotIndex Idx) {
404 iterator I = FindLiveRangeContaining(Idx);
408 /// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
409 VNInfo *getVNInfoAt(SlotIndex Idx) const {
410 const_iterator I = FindLiveRangeContaining(Idx);
415 /// necessarilly including Idx, or NULL. Use this to find the reaching def
417 VNInfo *getVNInfoBefore(SlotIndex Idx) const {
418 const_iterator I = FindLiveRangeContaining(Idx.getPrevSlot())
[all...] |
| /external/clang/unittests/AST/ |
| CommentParser.cpp | 94 size_t Idx,
99 if (Idx >= C->child_count())
101 << "Idx out of range. Idx = " << Idx
104 Comment::child_iterator I = C->child_begin() + Idx;
119 size_t Idx,
122 ::testing::AssertionResult AR = GetChildAt(C, Idx, TC);
140 size_t Idx,
143 ::testing::AssertionResult AR = GetChildAt(C, Idx, TC)
[all...] |
| /device/linaro/bootloader/edk2/OvmfPkg/SmmAccess/ |
| SmmAccessPei.c | 355 UINTN Idx;
362 for (Idx = 0; Idx < Count; ++Idx) {
364 SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,
365 SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));
|
| /external/llvm/include/llvm/IR/ |
| TypeFinder.h | 60 StructType *&operator[](unsigned Idx) { return StructTypes[Idx]; }
|
