| /frameworks/rs/rsov/compiler/spirit/ |
| visitor.h | 34 class Instruction;
52 virtual void visit(Instruction *) = 0;
72 // This visit(Instruction *) necessary?
73 virtual void visit(Instruction *inst);
86 void visit(INST_CLASS *inst) override { mAction((Instruction *)inst); }
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| instructions.h | 46 class Instruction : public Entity {
48 Instruction(uint32_t opCode) : mCodeAndCount(opCode) {}
49 Instruction(uint32_t opCode, uint32_t fixedWordCount)
51 virtual ~Instruction() {}
66 Instruction *addExtraOperand(uint32_t word) {
71 // Adds decoration to the current instruction.
72 // Returns: the result OpDecorate instruction
141 const std::vector<Instruction *> &getAnnotations() const {
151 std::vector<Instruction *> mDecorations;
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| /prebuilts/ndk/r13/sources/third_party/shaderc/third_party/spirv-tools/source/opt/ |
| passes.cpp | 36 module->ForEachInst([&modified](ir::Instruction* inst) {
|
| /art/compiler/optimizing/ |
| live_ranges_test.cc | 58 Instruction::CONST_4 | 0 | 0,
59 Instruction::RETURN);
74 // Last use is the return instruction.
105 Instruction::CONST_4 | 0 | 0,
106 Instruction::IF_EQ, 3,
107 Instruction::GOTO | 0x100,
108 Instruction::RETURN | 0 << 8);
122 // Last use is the return instruction.
156 Instruction::CONST_4 | 0 | 0,
157 Instruction::IF_EQ, 3
[all...] |
| /external/llvm/lib/Analysis/ |
| PHITransAddr.cpp | 25 static bool CanPHITrans(Instruction *Inst) {
34 if (Inst->getOpcode() == Instruction::Add &&
58 SmallVectorImpl<Instruction*> &InstInputs) {
59 // If this is a non-instruction value, there is nothing to do.
60 Instruction *I = dyn_cast<Instruction>(Expr);
63 // If it's an instruction, it is either in Tmp or its operands recursively
65 SmallVectorImpl<Instruction*>::iterator Entry =
75 errs() << "Instruction in PHITransAddr is not phi-translatable:\n";
81 // Validate the operands of the instruction
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 57 static void PrintOps(Instruction *I, const SmallVectorImpl<ValueEntry> &Ops) {
59 dbgs() << Instruction::getOpcodeName(I->getOpcode()) << " "
102 Instruction *I = dyn_cast<Instruction>(V);
105 if (I && (I->getOpcode() == Instruction::Or ||
106 I->getOpcode() == Instruction::And)) {
115 isOr = (I->getOpcode() == Instruction::Or);
126 /// Return true if V is an instruction of the specified opcode and if it
129 if (V->hasOneUse() && isa<Instruction>(V) &&
130 cast<Instruction>(V)->getOpcode() == Opcode &
[all...] |
| /art/runtime/interpreter/ |
| interpreter_switch_impl.cc | 64 // Code to run before each dex instruction.
119 const Instruction* inst = Instruction::At(insns + dex_pc);
130 case Instruction::NOP:
134 case Instruction::MOVE:
140 case Instruction::MOVE_FROM16:
146 case Instruction::MOVE_16:
152 case Instruction::MOVE_WIDE:
158 case Instruction::MOVE_WIDE_FROM16:
164 case Instruction::MOVE_WIDE_16
[all...] |
| /art/runtime/ |
| bytecode_utils.h | 38 const Instruction& CurrentInstruction() const { return *Instruction::At(code_ptr_); }
58 DexSwitchTable(const Instruction& instruction, uint32_t dex_pc)
59 : instruction_(instruction),
61 sparse_(instruction.Opcode() == Instruction::SPARSE_SWITCH) {
62 int32_t table_offset = instruction.VRegB_31t();
63 const uint16_t* table = reinterpret_cast<const uint16_t*>(&instruction) + table_offset;
64 DCHECK_EQ(table[0], sparse_ ? static_cast<uint16_t>(Instruction::kSparseSwitchSignature
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| PtrUseVisitor.h | 10 /// This file provides a collection of visitors which walk the (instruction)
67 /// \brief Get the instruction causing the visit to abort.
68 /// \returns a pointer to the instruction causing the abort if one is
70 Instruction *getAbortingInst() const { return AbortedInfo.getPointer(); }
72 /// \brief Get the instruction causing the pointer to escape.
73 /// \returns a pointer to the instruction which escapes the pointer if one
75 Instruction *getEscapingInst() const { return EscapedInfo.getPointer(); }
78 /// \param I The instruction which caused the visit to abort, if available.
79 void setAborted(Instruction *I = nullptr) {
85 /// \param I The instruction which escapes the pointer, if available
[all...] |
| LazyValueInfo.h | 27 class Instruction;
72 Instruction *CxtI = nullptr);
75 /// to be true or false at the specified instruction
78 Instruction *CxtI);
82 Constant *getConstant(Value *V, BasicBlock *BB, Instruction *CxtI = nullptr);
87 ConstantRange getConstantRange(Value *V, BasicBlock *BB, Instruction *CxtI = nullptr);
92 Instruction *CxtI = nullptr);
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXImageOptimizer.cpp | 31 SmallVector<Instruction*, 4> InstrToDelete;
39 bool replaceIsTypePSampler(Instruction &I);
40 bool replaceIsTypePSurface(Instruction &I);
41 bool replaceIsTypePTexture(Instruction &I);
43 void replaceWith(Instruction *From, ConstantInt *To);
64 Instruction &Instr = *I;
93 bool NVPTXImageOptimizer::replaceIsTypePSampler(Instruction &I) {
111 bool NVPTXImageOptimizer::replaceIsTypePSurface(Instruction &I) {
130 bool NVPTXImageOptimizer::replaceIsTypePTexture(Instruction &I) {
149 void NVPTXImageOptimizer::replaceWith(Instruction *From, ConstantInt *To)
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| LoopUtils.cpp | 36 bool RecurrenceDescriptor::areAllUsesIn(Instruction *I,
37 SmallPtrSetImpl<Instruction *> &Set) {
39 if (!Set.count(dyn_cast<Instruction>(*Use)))
76 Instruction *
78 SmallPtrSetImpl<Instruction *> &Visited,
79 SmallPtrSetImpl<Instruction *> &CI) {
84 Instruction *I, *J = cast<Instruction>(Phi->use_begin()->getUser());
102 Instruction *Start, Instruction *Exit, Type *RT, bool &IsSigned
[all...] |
| BypassSlowDivision.cpp | 74 // insertFastDiv - Substitutes the div/rem instruction with code that checks the
75 // value of the operands and uses a shorter-faster div/rem instruction when
76 // possible and the longer-slower div/rem instruction otherwise.
77 static bool insertFastDiv(Instruction *I, IntegerType *BypassType,
81 // Get instruction operands
117 Value *ShortDivisorV = FastBuilder.CreateCast(Instruction::Trunc, Divisor,
119 Value *ShortDividendV = FastBuilder.CreateCast(Instruction::Trunc, Dividend,
127 Value *FastQuotientV = FastBuilder.CreateCast(Instruction::ZExt,
130 Value *FastRemainderV = FastBuilder.CreateCast(Instruction::ZExt,
178 static bool reuseOrInsertFastDiv(Instruction *I, IntegerType *BypassType
[all...] |
| /art/disassembler/ |
| disassembler_arm64.cc | 44 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr,
61 void CustomDisassembler::VisitLoadLiteral(const Instruction* instr) {
100 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) {
112 const Instruction* instr = reinterpret_cast<const Instruction*>(begin);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 46 if (I->getOpcode() == Instruction::Shl) {
53 if (I->getOpcode() == Instruction::Mul) {
60 if (I->getOpcode() == Instruction::Add) {
79 /// If we find a cast of an allocation instruction, try to eliminate the cast by
81 Instruction *InstCombiner::PromoteCastOfAllocation(BitCastInst &CI,
149 // New is the allocation instruction, pointer typed. AI is the original
150 // allocation instruction, also pointer typed. Thus, cast to use is BitCast.
169 // Otherwise, it must be an instruction.
170 Instruction *I = cast<Instruction>(V)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| InstCombineSelect.cpp | 80 /// Assuming that the specified instruction is an operand to the select, return
81 /// a bitmask indicating which operands of this instruction are foldable if they
84 static unsigned GetSelectFoldableOperands(Instruction *I) {
86 case Instruction::Add:
87 case Instruction::Mul:
88 case Instruction::And:
89 case Instruction::Or:
90 case Instruction::Xor:
92 case Instruction::Sub: // Can only fold on the amount subtracted.
93 case Instruction::Shl: // Can only fold on the shift amount
[all...] |
| /external/v8/src/mips64/ |
| simulator-mips64.h | 128 inline Instruction* instr() const { return instr_; }
133 explicit SimInstructionBase(Instruction* instr) {}
136 Instruction* instr_;
147 explicit SimInstruction(Instruction* instr) { *this = instr; }
149 SimInstruction& operator=(Instruction* instr) {
205 // instruction.
304 void Format(Instruction* instr, const char* format);
312 inline uint16_t ReadHU(int64_t addr, Instruction* instr);
313 inline int16_t ReadH(int64_t addr, Instruction* instr);
315 inline void WriteH(int64_t addr, uint16_t value, Instruction* instr)
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLParser.h | 34 class Instruction;
96 // Instruction metadata resolution. Each instruction can have a list of
101 // instruction metadata kinds, such as dbg, get stored in the IR in an
111 SmallVector<Instruction*, 64> InstsWithTBAATag;
341 /// SetInstName - After an instruction is parsed and inserted into its
344 Instruction *Inst);
425 bool ParseInstructionMetadata(Instruction &Inst);
458 // Instruction Parsing. Each instruction parsing routine can return with
[all...] |
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| Constants.cpp | 194 case Instruction::UDiv:
195 case Instruction::SDiv:
196 case Instruction::FDiv:
197 case Instruction::URem:
198 case Instruction::SRem:
199 case Instruction::FRem:
252 if (CE->getOpcode() == Instruction::Sub) {
256 LHS->getOpcode() == Instruction::PtrToInt &&
257 RHS->getOpcode() == Instruction::PtrToInt &&
739 // can't be inline because we don't want to #include Instruction.h int
[all...] |
| Instructions.cpp | 10 // This file implements all of the non-inline methods for the LLVM instruction
33 Instruction *II(getInstruction());
87 : Instruction(PN.getType(), Instruction::PHI,
175 Instruction *InsertBefore)
176 : Instruction(RetTy, Instruction::LandingPad, 0, 0, InsertBefore) {
183 : Instruction(RetTy, Instruction::LandingPad, 0, 0, InsertAtEnd) {
188 : Instruction(LP.getType(), Instruction::LandingPad
[all...] |
| /external/llvm/lib/CodeGen/GlobalISel/ |
| IRTranslator.cpp | 64 bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) {
76 bool IRTranslator::translateReturn(const Instruction &Inst) {
80 // this is not important as a return is the last instruction
85 bool IRTranslator::translateBr(const Instruction &Inst) {
102 bool IRTranslator::translate(const Instruction &Inst) {
105 case Instruction::Add:
107 case Instruction::Or:
109 case Instruction::Br:
111 case Instruction::Ret:
150 for (const Instruction &Inst: BB)
[all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCContract.cpp | 77 bool tryToPeepholeInstruction(Function &F, Instruction *Inst,
79 SmallPtrSetImpl<Instruction *> &DepInsts,
83 bool optimizeRetainCall(Function &F, Instruction *Retain);
86 contractAutorelease(Function &F, Instruction *Autorelease,
88 SmallPtrSetImpl<Instruction *> &DependingInstructions,
91 void tryToContractReleaseIntoStoreStrong(Instruction *Release,
113 bool ObjCARCContract::optimizeRetainCall(Function &F, Instruction *Retain) {
115 const Instruction *Call = CS.getInstruction();
147 Function &F, Instruction *Autorelease, ARCInstKind Class,
148 SmallPtrSetImpl<Instruction *> &DependingInstructions
[all...] |
| /external/vixl/src/aarch64/ |
| instructions-aarch64.cc | 65 bool Instruction::IsLoad() const {
97 bool Instruction::IsStore() const {
127 uint64_t Instruction::GetImmLogical() const {
178 uint32_t Instruction::GetImmNEONabcdefgh() const {
183 float Instruction::Imm8ToFP32(uint32_t imm8) {
197 float Instruction::GetImmFP32() const { return Imm8ToFP32(GetImmFP()); }
200 double Instruction::Imm8ToFP64(uint32_t imm8) {
215 double Instruction::GetImmFP64() const { return Imm8ToFP64(GetImmFP()); }
218 float Instruction::GetImmNEONFP32() const {
223 double Instruction::GetImmNEONFP64() const
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_lowering_nvc0.cpp | 49 void handleDIV(Instruction *); // integer division, modulus
50 void handleRCPRSQ(Instruction *); // double precision float recip/rsqrt
57 NVC0LegalizeSSA::handleDIV(Instruction *i)
84 NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
99 Instruction *next;
100 for (Instruction *i = bb->getEntry(); i; i = next) {
130 void replaceZero(Instruction *);
131 void split64BitOp(Instruction *);
137 TexUse(Instruction *use, const Instruction *tex
[all...] |
| /external/v8/src/arm64/ |
| instructions-arm64.h | 86 // instruction (such as with fcvta). It cannot be set in FPCR.
97 class Instruction {
124 V8_INLINE const Instruction* following(int count = 1) const {
128 V8_INLINE Instruction* following(int count = 1) {
132 V8_INLINE const Instruction* preceding(int count = 1) const {
136 V8_INLINE Instruction* preceding(int count = 1) {
235 // does not check that the instruction actually has an Rd field.
264 // does not check that the instruction actually has an Rn field.
307 // The range of the branch instruction, expressed as 'instr +- range'.
354 // A marking nop is an instruction
[all...] |
