| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/DebugAgentTimerLib/ |
| DebugAgentTimerLib.c | 99 MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2));
|
| /device/linaro/bootloader/edk2/ArmPkg/Include/ |
| AsmMacroIoLib.h | 38 #define MmioOr32(_Address, _OrData) \
163 #define MmioOr32(Address, OrData) \
222 #define MmioOr32(Address, OrData) MmioOr32Macro Address, OrData
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/ |
| TimerLib.c | 37 MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/ |
| OmapDmaLib.c | 124 MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Sec/ |
| Sec.c | 53 MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
|
| /device/linaro/bootloader/edk2/BeagleBoardPkg/Sec/ |
| Sec.c | 53 MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/Omap35xxTimerLib/ |
| TimerLib.c | 37 MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/ |
| OmapDmaLib.c | 124 MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchAccess.h | 76 MmioOr32 ( \
184 MmioOr32 ( \
287 MmioOr32 ( \
389 #define PchMmRcrb32Or(Register, OrData) MmioOr32 (PCH_RCRB_BASE + Register, OrData)
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/MonoStatusCode/ |
| PlatformStatusCode.c | 357 MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L
359 MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| PchInitPeim.c | 141 MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_PWROK_FLR);
149 MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR);
457 MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, BIT24);
463 MmioOr32 (IO_BASE_ADDRESS + 0x0520, 0x01); // UART3_RXD-L
464 MmioOr32 (IO_BASE_ADDRESS + 0x0530, 0x01); // UART3_TXD-0
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Library/PL031RealTimeClockLib/ |
| PL031RealTimeClockLib.c | 94 MmioOr32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);
99 MmioOr32 (mPL031RtcBase + PL031_RTC_ICR_IRQ_CLEAR_REGISTER, PL031_CLEAR_IRQ);
104 MmioOr32 (mPL031RtcBase + PL031_RTC_CR_CONTROL_REGISTER, PL031_RTC_ENABLED);
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/TimerDxe/ |
| Timer.c | 360 MmioOr32 (CM_FCLKEN_PER, CM_FCLKEN_PER_EN_GPT3_ENABLE);
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV3/ |
| ArmGicV3Dxe.c | 258 MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/SP804TimerDxe/ |
| SP804Timer.c | 230 MmioOr32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/TimerDxe/ |
| Timer.c | 360 MmioOr32 (CM_FCLKEN_PER, CM_FCLKEN_PER_EN_GPT3_ENABLE);
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/InterruptDxe/ |
| HardwareInterrupt.c | 326 MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/InterruptDxe/ |
| HardwareInterrupt.c | 326 MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| Platform.c | 462 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
464 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
481 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
489 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/PciEmulation/ |
| PciEmulation.c | 595 MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
|
| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/BaseCachingPciExpressLib/ |
| PciExpressLib.c | 935 return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/ |
| PciLib.c | 886 return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Library/BasePciExpressLib/ |
| PciExpressLib.c | 925 return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/PciEmulation/ |
| PciEmulation.c | 595 MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/ |
| EdkIIGlueIoLib.h | [all...] |
