| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfoImpl.h | 47 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) {
48 switch (Opcode) {
260 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
267 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
293 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
306 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { return 1; }
308 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst,
313 unsigned getCFInstrCost(unsigned Opcode) { return 1; }
315 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) {
319 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
| FieldFlagChanger.java | 26 import dexfuzz.rawdex.Opcode;
156 Opcode opcode = mInsn.insn.info.opcode; local
157 if (Opcode.isBetween(opcode, Opcode.IGET, Opcode.SPUT_SHORT)) {
|
| NonsenseStringPrinter.java | 25 import dexfuzz.rawdex.Opcode;
123 constStringInsn.insn.info = Instruction.getOpcodeInfo(Opcode.CONST_STRING);
129 streamLoadInsn.insn.info = Instruction.getOpcodeInfo(Opcode.SGET_OBJECT);
135 invokeInsn.insn.info = Instruction.getOpcodeInfo(Opcode.INVOKE_VIRTUAL_RANGE);
|
| /external/llvm/lib/IR/ |
| ConstantsContext.h | 41 UnaryConstantExpr(unsigned Opcode, Constant *C, Type *Ty)
42 : ConstantExpr(Ty, Opcode, &Op<0>(), 1) {
58 BinaryConstantExpr(unsigned Opcode, Constant *C1, Constant *C2,
60 : ConstantExpr(C1->getType(), Opcode, &Op<0>(), 2) {
441 uint8_t Opcode;
448 ConstantExprKeyType(unsigned Opcode, ArrayRef<Constant *> Ops,
453 : Opcode(Opcode), SubclassOptionalData(SubclassOptionalData),
457 : Opcode(CE->getOpcode()),
463 : Opcode(CE->getOpcode())
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.cpp | 88 bool R600InstrInfo::isMov(unsigned Opcode) const {
89 switch(Opcode) {
101 // an opcode falls into this category.
102 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
103 switch (Opcode) {
110 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
114 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
115 switch(Opcode) {
125 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
126 unsigned TargetFlags = get(Opcode).TSFlags
[all...] |
| /external/swiftshader/src/Shader/ |
| Shader.hpp | 35 enum Opcode
273 static Opcode OPCODE_DP(int);
274 static Opcode OPCODE_LEN(int);
275 static Opcode OPCODE_DIST(int);
276 static Opcode OPCODE_NRM(int);
277 static Opcode OPCODE_FORWARD(int);
278 static Opcode OPCODE_REFLECT(int);
279 static Opcode OPCODE_REFRACT(int);
480 explicit Instruction(Opcode opcode);
503 Opcode opcode; member in struct:sw::Shader::Instruction
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MCExpr.h | 230 enum Opcode {
238 Opcode Op;
241 MCUnaryExpr(Opcode _Op, const MCExpr *_Expr)
248 static const MCUnaryExpr *Create(Opcode Op, const MCExpr *Expr,
268 Opcode getOpcode() const { return Op; }
284 enum Opcode {
310 Opcode Op;
313 MCBinaryExpr(Opcode _Op, const MCExpr *_LHS, const MCExpr *_RHS)
320 static const MCBinaryExpr *Create(Opcode Op, const MCExpr *LHS,
400 Opcode getOpcode() const { return Op;
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 42 c->Program.Instructions.U.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE;
119 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
122 for (i = 0; i < opcode->NumSrcRegs; ++i) {
127 if (opcode->HasDstReg) {
145 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
148 for(i = 0; i < opcode->NumSrcRegs; ++i) {
177 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
200 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
300 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
344 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Sample/Tools/Source/GenDepex/ |
| GenDepex.c | 57 PUSH opcode - 1 byte
59 PUSH opcode - 1 byte
61 AND opcode - 1 byte
62 NOT opcode - 1 byte
63 PUSH opcode - 1 byte
65 OR opcode - 1 byte
66 END opcode - 1 byte
178 Pop an element from the Opcode stack.
182 Stack Current top of the OpCode stack location
186 DEPENDENCY_OPCODE OpCode at the top of the OpCode stack.
[all...] |
| /external/javassist/src/main/javassist/compiler/ |
| Javac.java | 31 import javassist.bytecode.Opcode;
238 if (op == Opcode.DRETURN)
239 value = Opcode.DCONST_0;
240 else if (op == Opcode.FRETURN)
241 value = Opcode.FCONST_0;
242 else if (op == Opcode.LRETURN)
243 value = Opcode.LCONST_0;
244 else if (op == Opcode.RETURN)
245 value = Opcode.NOP;
247 value = Opcode.ICONST_0
[all...] |
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_optimize.c | 65 static boolean has_destination(unsigned opcode)
67 return (opcode != TGSI_OPCODE_NOP &&
68 opcode != TGSI_OPCODE_KIL &&
69 opcode != TGSI_OPCODE_KILP &&
70 opcode != TGSI_OPCODE_END &&
71 opcode != TGSI_OPCODE_RET);
88 static boolean op_commutes(unsigned opcode)
90 switch(opcode)
102 static unsigned op_neutral_element(unsigned opcode)
104 switch(opcode)
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 56 unsigned Opcode = MI->getOpcode();
58 if (Opcode == AArch64::SYSxt)
65 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
66 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
72 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
73 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 765 unsigned Opcode = MI.getOpcode();
766 switch (Opcode) {
794 unsigned Opcode;
798 case AArch64::ADDWrr: Opcode = AArch64::ADDWrs; break;
799 case AArch64::SUBWrr: Opcode = AArch64::SUBWrs; break;
800 case AArch64::ADDXrr: Opcode = AArch64::ADDXrs; break;
801 case AArch64::SUBXrr: Opcode = AArch64::SUBXrs; break;
802 case AArch64::ADDSWrr: Opcode = AArch64::ADDSWrs; break;
803 case AArch64::SUBSWrr: Opcode = AArch64::SUBSWrs; break;
804 case AArch64::ADDSXrr: Opcode = AArch64::ADDSXrs; break
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 221 unsigned Opcode = I->getOpcode();
222 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
223 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
224 bool UseSignedOp = Opcode == Instruction::SDiv ||
225 Opcode == Instruction::SRem;
|
| /frameworks/native/libs/vr/libvrflinger/ |
| display_service.cpp | 56 ALOGD_IF(TRACE, "DisplayService::HandleMessage: opcode=%d", message.GetOp());
58 case DisplayProtocol::GetMetrics::Opcode:
63 case DisplayProtocol::CreateSurface::Opcode:
68 case DisplayProtocol::GetNamedBuffer::Opcode:
73 case DisplayProtocol::IsVrAppRunning::Opcode:
79 case DisplayProtocol::SetAttributes::Opcode:
80 case DisplayProtocol::CreateQueue::Opcode:
81 case DisplayProtocol::GetSurfaceInfo::Opcode:
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 210 /// Pool allocation for machine-opcode SDNode operands.
757 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
759 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
761 SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT> ResultTys,
763 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,
767 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
768 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N);
769 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
771 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
773 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 54 unsigned Opcode = Mips::Mflo16;
55 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
59 unsigned Opcode = Mips::Mfhi16;
60 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
180 unsigned Opcode = Node->getOpcode();
190 switch (Opcode) {
204 if (Opcode == ISD::ADDE) {
232 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
247 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 281 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
285 const MCInstrDesc &MCID = DAG.TII->get(Opcode);
336 unsigned Opcode = MI->getOpcode();
339 GetInstrType(Opcode, isFirst, isSingle, isCracked,
373 if (HasCTRSet && Opcode == PPC::BCTRL)
394 unsigned Opcode = MI->getOpcode();
397 GetInstrType(Opcode, isFirst, isSingle, isCracked,
402 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
|
| /art/compiler/dex/ |
| inline_method_analyser.cc | 60 template <Instruction::Code opcode> bool Opcode();
112 template <Instruction::Code opcode>
113 bool Matcher::Opcode() {
114 return instruction_->Opcode() == opcode;
119 return IsInstructionDirectConst(instruction_->Opcode()) &&
120 (instruction_->Opcode() == Instruction::CONST_WIDE ? instruction_->VRegB_51l() == 0
126 return IsInstructionIPut(instruction_->Opcode()) &&
144 DCHECK_EQ(invoke_direct->Opcode(), Instruction::INVOKE_DIRECT)
449 Instruction::Code opcode = instruction->Opcode(); local
577 Instruction::Code opcode = instruction->Opcode(); local
641 Instruction::Code opcode = instruction->Opcode(); local
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
70 BuildMI(MBB, I, dl, TII.get(Opcode))
127 int Opcode;
129 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
134 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
136 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
264 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
265 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize)
[all...] |
| /frameworks/native/services/vr/bufferhubd/ |
| consumer_queue_channel.cpp | 43 case BufferHubRPC::CreateConsumerQueue::Opcode:
48 case BufferHubRPC::GetQueueInfo::Opcode:
53 case BufferHubRPC::ConsumerQueueImportBuffers::Opcode:
|
| /art/tools/dexfuzz/src/dexfuzz/rawdex/ |
| Opcode.java | 19 public enum Opcode {
277 public static boolean isBetween(Opcode opcode, Opcode opcode1, Opcode opcode2) {
278 return (opcode.ordinal() >= opcode1.ordinal() && opcode.ordinal() <= opcode2.ordinal());
|
| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| IRTranslator.h | 96 /// Translate \p Inst into a binary operation \p Opcode.
98 bool translateBinaryOp(unsigned Opcode, const Instruction &Inst);
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 151 unsigned Opcode;
156 MCInst() : Opcode(0) {}
158 void setOpcode(unsigned Op) { Opcode = Op; }
159 unsigned getOpcode() const { return Opcode; }
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 53 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
61 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
67 if ((Opcode == Instruction::SDiv || Opcode == Instruction::UDiv ||
68 Opcode == Instruction::SRem || Opcode == Instruction::URem) &&
76 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
77 int ISD = TLI->InstructionOpcodeToISD(Opcode);
78 assert(ISD && "Invalid opcode");
99 return BaseT::getCastInstrCost(Opcode, Dst, Src)
[all...] |
