| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| PTXInstPrinter.cpp | 36 StringRef PTXInstPrinter::getOpcodeName(unsigned Opcode) const {
37 return getInstructionName(Opcode);
|
| /art/compiler/dex/ |
| verified_method.cc | 70 Instruction::Code code = inst->Opcode();
|
| /art/tools/dexfuzz/src/dexfuzz/program/ |
| MutatableCode.java | 21 import dexfuzz.rawdex.Opcode;
377 moveInsn.insn.info = Instruction.getOpcodeInfo(Opcode.MOVE_OBJECT_16);
379 moveInsn.insn.info = Instruction.getOpcodeInfo(Opcode.MOVE_WIDE_16);
382 moveInsn.insn.info = Instruction.getOpcodeInfo(Opcode.MOVE_16);
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| DivZeroChecker.cpp | 50 BinaryOperator::Opcode Op = B->getOpcode();
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.cpp | 143 BinaryOperator::Opcode op = SE->getOpcode();
159 BinaryOperator::Opcode Op = SSE->getOpcode();
232 BinaryOperator::Opcode Op = SE->getOpcode();
248 BinaryOperator::Opcode op,
|
| /external/javassist/src/main/javassist/expr/ |
| Handler.java | 127 b.addOpcode(Opcode.GOTO);
|
| /external/javassist/src/main/javassist/util/proxy/ |
| ProxyFactory.java | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 179 unsigned computeInstrLatency(unsigned Opcode) const;
|
| /external/llvm/include/llvm/MC/ |
| MCInstPrinter.h | 75 /// \brief Return the name of the specified opcode enum (e.g. "MOV32ri") or
77 StringRef getOpcodeName(unsigned Opcode) const;
|
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.h | 43 const char *getTargetNodeName(unsigned Opcode) const override;
|
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 35 /// The opcode of the instruction, as used in an MCInst
43 /// The opcode field from the record; this is the opcode used in the Intel
45 uint8_t Opcode;
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_pair_dead_sources.c | 24 const struct rc_opcode_info * info = rc_get_opcode_info(sub->Opcode);
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| AnalyzedInstruction.java | 36 import org.jf.dexlib2.Opcode;
367 if (instruction.getOpcode() == Opcode.IF_EQZ || instruction.getOpcode() == Opcode.IF_NEZ) {
371 previousInstruction.instruction.getOpcode() == Opcode.INSTANCE_OF &&
|
| /external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/ |
| AddrModeMatcher.h | 99 bool MatchOperationAddr(User *Operation, unsigned Opcode, unsigned Depth);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.h | 52 const char *getTargetNodeName(unsigned Opcode) const;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelLowering.h | 63 virtual const char *getTargetNodeName(unsigned Opcode) const;
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
59 if (Opcode == XCore::LDWFI)
80 int Opcode = MI->getOpcode();
81 if (Opcode == XCore::STWFI)
129 /// the correspondent Branch instruction opcode.
142 /// opcode that matches the cc.
398 /// ReverseBranchCondition - Return the inverse opcode of the
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| X86RecognizableInstr.h | 38 /// The opcode of the instruction, as used in an MCInst
44 /// The opcode field from the record; this is the opcode used in the Intel
46 uint8_t Opcode;
|
| /external/v8/src/arm/ |
| constants-arm.h | 140 enum Opcode {
577 return static_cast<Opcode>(Bits(24, 21));
579 inline Opcode OpcodeField() const {
580 return static_cast<Opcode>(BitField(24, 21));
|
| /frameworks/native/libs/vr/libpdx_uds/ |
| remote_method_tests.cpp | 347 case TestInterface::Add::Opcode:
352 case TestInterface::Foo::Opcode:
357 case TestInterface::Concatenate::Opcode:
362 case TestInterface::SumVector::Opcode:
367 case TestInterface::StringLength::Opcode:
372 case TestInterface::SendTestType::Opcode:
377 case TestInterface::SendVector::Opcode:
382 case TestInterface::Rot13::Opcode:
387 case TestInterface::NoArgs::Opcode:
392 case TestInterface::SendFile::Opcode
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 274 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
841 int Opcode = Inst.getOpcode();
842 switch (Opcode) {
848 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
851 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
927 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
941 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
955 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 235 // Opcode is the opcode of an instruction that has an address operand,
237 // address that has displacement Offset. Return the opcode of a suitable
238 // instruction (which might be Opcode itself) or 0 if no such instruction
240 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
242 // If Opcode is a load instruction that has a LOAD AND TEST form,
243 // return the opcode for the testing form, otherwise return 0.
244 unsigned getLoadAndTest(unsigned Opcode) const;
252 // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_program.c | 180 if (prog->Instructions[i].Opcode == OPCODE_CAL) {
188 if (prog->Instructions[i].Opcode == OPCODE_RET) {
195 for (r = 0; r < _mesa_num_inst_src_regs(inst->Opcode); r++) {
|
| brw_wm_fp.c | 220 inst->Opcode = op;
248 * We'd rather not have to support that splatting in the opcode implementations,
250 * anyway. We can easily get both by emitting the opcode to one channel, and
897 assert(inst->Opcode == OPCODE_TXP);
1014 GLuint nr_args = brw_wm_nr_args( inst->Opcode );
1033 if (insn->Opcode < MAX_OPCODE)
1035 else if (insn->Opcode < MAX_WM_OPCODE) {
1036 GLuint idx = insn->Opcode - MAX_OPCODE;
1042 printf("965 Opcode %d\n", insn->Opcode);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86CodeEmitter.cpp | 593 unsigned Opcode) {
594 const MCInstrDesc *Desc = &II->get(Opcode);
628 unsigned Opcode = Desc->Opcode;
630 // Emit the lock opcode prefix as needed.
634 // Emit segment override opcode prefix as needed.
646 // Emit the repeat opcode prefix as needed.
650 // Emit the operand size opcode prefix as needed.
654 // Emit the address size opcode prefix as needed.
660 case X86II::TB: // Two-byte opcode prefi
[all...] |
