| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/gen/ |
| MIPS64Ops.go | 54 "R20",
130 gp = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31")
|
| MIPSOps.go | 53 "R20",
114 gp = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31")
|
| PPC64Ops.go | 40 "R20",
123 gp = buildReg("R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29")
|
| ARM64Ops.go | 53 "R20",
126 gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30")
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 674 case Hexagon::R20:
[all...] |
| HexagonMCInstrInfo.cpp | 232 case R20:
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/gen/ |
| ARM64Ops.go | 53 "R20",
126 gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30")
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 40 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
51 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
[all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 497 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 403 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 778 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 147 {PPC::R20, -48},
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
| /prebuilts/go/darwin-x86/src/reflect/ |
| all_test.go | [all...] |
| /prebuilts/go/linux-x86/src/reflect/ |
| all_test.go | [all...] |
