| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 332 .addReg(PPC::R31)
437 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
443 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
456 // If there is a frame pointer, copy R1 into R31
459 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
474 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
582 // value of R31 in this case.
586 .addReg(PPC::R31).addImm(FrameSize);
595 .addReg(PPC::R31)
649 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
[all...] |
| PPCRegisterInfo.cpp | 110 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
136 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
244 // Note that this is over conservative, as it also prevents allocation of R31
248 Reserved.set(PPC::R31);
271 Reserved.set(PPC::R31);
383 .addReg(PPC::R31)
547 PPC::R31 : PPC::R1,
634 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
|
| /prebuilts/go/darwin-x86/src/runtime/ |
| asm_mipsx.s | 98 MOVW R31, gobuf_pc(R1)
128 MOVW gobuf_lr(R3), R31
145 MOVW R31, (g_sched+gobuf_pc)(g)
172 JAL (R31) // make sure this function is not leaf
262 MOVW R31, (g_sched+gobuf_pc)(g)
435 MOVW 0(R29), R31
436 ADDU $-8, R31
447 MOVW R31, (g_sched+gobuf_pc)(g)
928 MOVW R31, R10 // this call frame does not save LR
937 MOVW R10, R31
[all...] |
| /prebuilts/go/linux-x86/src/runtime/ |
| asm_mipsx.s | 98 MOVW R31, gobuf_pc(R1)
128 MOVW gobuf_lr(R3), R31
145 MOVW R31, (g_sched+gobuf_pc)(g)
172 JAL (R31) // make sure this function is not leaf
262 MOVW R31, (g_sched+gobuf_pc)(g)
435 MOVW 0(R29), R31
436 ADDU $-8, R31
447 MOVW R31, (g_sched+gobuf_pc)(g)
928 MOVW R31, R10 // this call frame does not save LR
937 MOVW R10, R31
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaInstrInfo.cpp | 322 BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
323 .addReg(Alpha::R31)
324 .addReg(Alpha::R31);
|
| AlphaISelDAGToDAG.cpp | 260 Alpha::R31, MVT::i64);
351 CurDAG->getRegister(Alpha::R31, MVT::i64),
|
| AlphaRegisterInfo.cpp | 76 Reserved.set(Alpha::R31);
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 59 // MBlaze callee-save register range is R20 - R31
63 MBlaze::R28, MBlaze::R29, MBlaze::R30, MBlaze::R31,
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/ |
| inst.go | 94 R31
228 case R0 <= r && r <= R31:
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/ |
| inst.go | 94 R31
228 case R0 <= r && r <= R31:
|
| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/ |
| operand_test.go | 486 {"R31", "R31"},
618 {"R31", "R31"},
701 {"R31", "R31"},
|
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/ |
| operand_test.go | 486 {"R31", "R31"},
618 {"R31", "R31"},
701 {"R31", "R31"},
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 224 // [if ([!]p0[.new])] jumpr r31
266 // jumpr r31
267 // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
269 if (Hexagon::R31 == DstReg) {
286 // [if ([!]p0[.new])] jumpr r31
288 (Hexagon::R31 == DstReg)) {
624 // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb).
627 (MIb.getOperand(1).getReg() == Hexagon::R31))
630 (MIb.getOperand(0).getReg() == Hexagon::R31))
816 break; // none SUBInst jumpr r31
[all...] |
| HexagonMCTargetDesc.cpp | 100 InitHexagonMCRegisterInfo(X, Hexagon::R31);
|
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.cpp | 161 Lanai::R30, Lanai::R31};
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/gen/ |
| MIPS64Ops.go | 65 "R31", // aka REGLINK
130 gp = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31")
285 clobbers: buildReg("R1 R31"),
379 linkreg: int8(num["R31"]),
|
| MIPSOps.go | 64 "R31", // REGLINK
114 gp = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31")
411 linkreg: int8(num["R31"]),
|
| PPC64Ops.go | 17 // register (R31).
51 "R31", // REGTMP
131 tmp = buildReg("R31")
|
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/gen/ |
| MIPS64Ops.go | 65 "R31", // aka REGLINK
130 gp = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31")
285 clobbers: buildReg("R1 R31"),
379 linkreg: int8(num["R31"]),
|
| MIPSOps.go | 64 "R31", // REGLINK
114 gp = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31")
411 linkreg: int8(num["R31"]),
|
| PPC64Ops.go | 17 // register (R31).
51 "R31", // REGTMP
131 tmp = buildReg("R31")
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 85 case SPU::R31: return 31;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 100 static const SpillSlot darwinOffsets = {PPC::R31, -4};
136 {PPC::R31, -4},
520 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
749 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
[all...] |
| PPCRegisterInfo.cpp | 261 Reserved.set(PPC::R31);
387 .addReg(PPC::R31)
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Efi/Protocol/DebugSupport/ |
| DebugSupport.h | 354 UINT64 R31;
465 // virtual registers - nat bits for R1-R31
|
