| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ScheduleDAGPrinter.cpp | 46 static bool hasNodeAddressLabel(const SUnit *Node,
53 static std::string getEdgeAttributes(const SUnit *Node,
64 std::string getNodeLabel(const SUnit *Node, const ScheduleDAG *Graph);
65 static std::string getNodeAttributes(const SUnit *N,
77 std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
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| ScheduleDAGInstrs.h | 111 std::vector<std::vector<SUnit *> > Defs;
112 std::vector<std::vector<SUnit *> > Uses;
117 std::vector<SUnit *> PendingLoads;
148 /// NewSUnit - Creates a new SUnit and return a ptr to it.
150 SUnit *NewSUnit(MachineInstr *MI) {
152 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
154 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
183 virtual void ComputeLatency(SUnit *SU);
188 virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use
[all...] |
| AntiDepBreaker.h | 45 virtual unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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| ScheduleDAGInstrs.cpp | 189 // We'll be allocating one SUnit for each instruction, plus one for
197 SUnit *BarrierChain = 0, *AliasChain = 0;
203 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
204 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
244 // Create the SUnit for this MI.
245 SUnit *SU = NewSUnit(MI);
264 std::vector<SUnit *> &UseList = Uses[Reg];
266 std::vector<SUnit *> &DefList = Defs[Reg];
276 SUnit *DefSU = DefList[i];
285 std::vector<SUnit *> &MemDefList = Defs[*Alias]
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 125 std::vector<SUnit*> PendingQueue;
144 std::unique_ptr<SUnit*[]> LiveRegDefs;
145 std::unique_ptr<SUnit*[]> LiveRegGens;
148 // Each interference is an SUnit and set of physical registers.
149 SmallVector<SUnit*, 4> Interferences;
150 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT;
159 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
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| ScheduleDAGVLIW.cpp | 62 std::vector<SUnit*> PendingQueue;
87 void releaseSucc(SUnit *SU, const SDep &D);
88 void releaseSuccessors(SUnit *SU);
89 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
117 SUnit *SuccSU = D.getSUnit();
140 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) {
142 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
154 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
186 std::vector<SUnit*> NotReady
[all...] |
| ResourcePriorityQueue.cpp | 70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
77 SUnit *PredSU = I->getSUnit();
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
115 SUnit *SuccSU = I->getSUnit();
145 static unsigned numberCtrlDepsInSU(SUnit *SU) {
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
155 static unsigned numberCtrlPredInSU(SUnit *SU) {
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end()
[all...] |
| ScheduleDAGFast.cpp | 49 SmallVector<SUnit *, 16> Queue;
53 void push(SUnit *U) {
57 SUnit *pop() {
59 SUnit *V = Queue.back();
77 std::vector<SUnit*> LiveRegDefs;
86 /// AddPred - adds a predecessor edge to SUnit SU.
88 void AddPred(SUnit *SU, const SDep &D) {
92 /// RemovePred - removes a predecessor edge from SUnit SU.
94 void RemovePred(SUnit *SU, const SDep &D) {
99 void ReleasePred(SUnit *SU, SDep *PredEdge)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| GCNHazardRecognizer.h | 50 void EmitInstruction(SUnit *SU) override;
52 HazardType getHazardType(SUnit *SU, int Stalls) override;
54 unsigned PreEmitNoops(SUnit *SU) override;
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| R600MachineScheduler.cpp | 45 void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc,
46 std::vector<SUnit *> &QDst)
57 SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
58 SUnit *SU = nullptr;
134 const SUnit &S = DAG->SUnits[i];
144 void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
192 void R600SchedStrategy::releaseTopNode(SUnit *SU) {
196 void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
222 R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
295 int R600SchedStrategy::getInstKind(SUnit* SU)
[all...] |
| SIMachineScheduler.h | 56 std::vector<SUnit*> SUnits;
58 std::vector<SUnit*> TopReadySUs;
59 std::vector<SUnit*> ScheduledSUnits;
106 void addUnit(SUnit *SU);
137 std::vector<SUnit*> getScheduledUnits() { return ScheduledSUnits; }
163 // The best SUnit candidate.
164 SUnit *SU;
192 void undoReleaseSucc(SUnit *SU, SDep *SuccEdge);
193 void releaseSucc(SUnit *SU, SDep *SuccEdge);
196 void releaseSuccessors(SUnit *SU, bool InOrOutBlock)
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| SIMachineScheduler.cpp | 178 void SIScheduleBlock::addUnit(SUnit *SU) {
242 SUnit* SIScheduleBlock::pickNode() {
245 for (SUnit* SU : TopReadySUs) {
273 for (SUnit* SU : SUnits) {
279 SUnit *SU = TopReadySUs[0];
317 for (SUnit* SU : ScheduledSUnits) {
391 for (SUnit* SU : SUnits) {
397 SUnit *SU = pickNode();
411 for (SUnit* SU : SUnits) {
421 for (SUnit* SU : SUnits)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGList.cpp | 59 std::vector<SUnit*> PendingQueue;
81 void ReleaseSucc(SUnit *SU, const SDep &D);
82 void ReleaseSuccessors(SUnit *SU);
83 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
108 void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
109 SUnit *SuccSU = D.getSUnit();
129 void ScheduleDAGList::ReleaseSuccessors(SUnit *SU) {
131 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
143 void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
175 std::vector<SUnit*> NotReady
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| DFAPacketizer.h | 42 class SUnit;
142 std::map<MachineInstr*, SUnit*> MIToSUnit;
195 virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
200 virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
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| ScoreboardHazardRecognizer.h | 28 class SUnit;
115 HazardType getHazardType(SUnit *SU, int Stalls) override;
117 void EmitInstruction(SUnit *SU) override;
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| ScheduleDFS.h | 26 class SUnit;
71 /// \brief Per-SUnit data computed during DFS for various metrics.
102 /// DFS results for each SUnit in this DAG.
142 void compute(ArrayRef<SUnit> SUnits);
146 unsigned getNumInstrs(const SUnit *SU) const {
159 ILPValue getILP(const SUnit *SU) const {
170 unsigned getSubtreeID(const SUnit *SU) const {
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 45 virtual HazardType getHazardType(SUnit *SU, int Stalls);
47 virtual void EmitInstruction(SUnit *SU);
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 51 virtual HazardType getHazardType(SUnit *SU, int Stalls);
52 virtual void EmitInstruction(SUnit *SU);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.h | 62 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
66 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
81 bool canPromoteToDotCur(const MachineInstr* MI, const SUnit* PacketSU,
89 bool canPromoteToDotNew(const MachineInstr* MI, const SUnit* PacketSU,
92 bool canPromoteToNewValue(const MachineInstr* MI, const SUnit* PacketSU,
|
| HexagonMachineScheduler.cpp | 25 SUnit* LastSequentialCall = nullptr;
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
68 for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(),
83 bool VLIWResourceModel::reserveResources(SUnit *SU) {
156 SmallVector<SUnit*, 8> TopRoots, BotRoots;
164 // FIXME: SUnit::dumpAll always recompute depth and height now. The max
184 SUnit *SU = SchedImpl->pickNode(IsTopNode);
228 void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) {
232 for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end();
245 void ConvergingVLIWScheduler::releaseBottomNode(SUnit *SU)
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 29 class SUnit;
118 virtual HazardType getHazardType(SUnit *SU, int Stalls);
120 virtual void EmitInstruction(SUnit *SU);
|
| /external/llvm/lib/CodeGen/ |
| MachinePipeliner.cpp | 220 SetVector<SUnit *> NodeOrder;
228 DenseMap<SUnit *, std::pair<unsigned, int64_t>> InstrChanges;
236 std::vector<SUnit> &SUnits;
237 SetVector<SUnit *> Stack;
239 SmallVector<SmallPtrSet<SUnit *, 4>, 10> B;
245 Circuits(std::vector<SUnit> &SUs)
252 B.assign(SUnits.size(), SmallPtrSet<SUnit *, 4>());
274 int getASAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ASAP; }
277 int getALAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ALAP; }
281 int getMOV(SUnit *Node) { return getALAP(Node) - getASAP(Node);
[all...] |
| AntiDepBreaker.h | 42 virtual unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
|
| MachineScheduler.cpp | 533 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
537 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
554 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
555 SUnit *SuccSU = SuccEdge->getSUnit();
582 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
583 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
593 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
594 SUnit *PredSU = PredEdge->getSUnit();
621 void ScheduleDAGMI::releasePredecessors(SUnit *SU)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSubtargetInfo.h | 32 class SUnit;
160 virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
|
