| /external/mesa3d/src/mesa/swrast/ |
| s_stencil.c | 132 const GLubyte wrtmask = ctx->Stencil.WriteMask[face];
500 const GLuint stencilMask = ctx->Stencil.WriteMask[0];
525 /* need to apply writemask */
554 const GLuint writeMask = ctx->Stencil.WriteMask[0];
561 if (!rb || writeMask == 0)
571 if ((writeMask & stencilMax) != stencilMax) {
590 GLubyte clear = ctx->Stencil.Clear & writeMask & 0xff;
591 GLubyte mask = (~writeMask) & 0xff;
617 GLuint clear = (ctx->Stencil.Clear & writeMask & 0xff) << 24
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| r500_fragprog.c | 109 inst_mov->U.I.DstReg.WriteMask = 0;
159 writer->Inst->U.I.DstReg.WriteMask = 0;
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| radeon_vert_fc.c | 32 dst->WriteMask = RC_MASK_W;
|
| r500_fragprog_emit.c | 269 code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11);
270 code->inst[ip].inst0 |= inst->Alpha.WriteMask ? 1 << 14 : 0;
384 | (inst->DstReg.WriteMask << 11)
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| /external/mesa3d/src/mesa/drivers/common/ |
| driverfuncs.c | 309 ctx->Driver.StencilMaskSeparate(ctx, GL_FRONT, ctx->Stencil.WriteMask[0]);
310 ctx->Driver.StencilMaskSeparate(ctx, GL_BACK, ctx->Stencil.WriteMask[1]);
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_exec.h | 52 ((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
|
| tgsi_ureg.h | 75 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
[all...] |
| tgsi_scan.c | 321 dst->Register.WriteMask != TGSI_WRITEMASK_XYZW)
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| tgsi_build.c | 889 dst_register.WriteMask = TGSI_WRITEMASK_XYZW;
915 dst_register.WriteMask = mask;
1071 reg->Register.WriteMask,
[all...] |
| tgsi_sanity.c | 347 if (!inst->Dst[i].Register.WriteMask) {
348 report_error(ctx, "Destination register has empty writemask");
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| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc.h | 267 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
|
| /external/mesa3d/src/gallium/include/pipe/ |
| p_shader_tokens.h | 601 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i915_state.c | 68 front_writemask = ctx->Stencil.WriteMask[0];
75 back_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
83 front_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
90 back_writemask = ctx->Stencil.WriteMask[0];
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vs_constval.c | 69 set_active_component( t, dst.File, dst.Index, active & dst.WriteMask );
|
| brw_wm.c | 520 if (ctx->Stencil.WriteMask[0] ||
521 ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
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| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| nv10_state_raster.c | 158 PUSH_DATA (push, ctx->Stencil.WriteMask[0]);
|
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.h | 71 * Writemask values, 1 bit per component.
300 GLuint WriteMask:4;
|
| program_parse.y | 637 $$.WriteMask = $2.mask;
662 $$.WriteMask = $2.mask;
[all...] |
| prog_print.c | 523 _mesa_writemask_string(GLuint writeMask)
528 if (writeMask == WRITEMASK_XYZW)
532 if (writeMask & WRITEMASK_X)
534 if (writeMask & WRITEMASK_Y)
536 if (writeMask & WRITEMASK_Z)
538 if (writeMask & WRITEMASK_W)
574 _mesa_writemask_string(dstReg->WriteMask));
587 _mesa_writemask_string(dstReg->WriteMask));
[all...] |
| program.c | 1037 inst->DstReg.WriteMask = WRITEMASK_XYZW;
[all...] |
| /external/mesa3d/src/mesa/main/ |
| nvprogram.c | 540 inst->DstReg.WriteMask = WRITEMASK_XYZW;
553 inst->DstReg.WriteMask = WRITEMASK_XYZW;
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| /external/mesa3d/src/mesa/state_tracker/ |
| st_mesa_to_tgsi.c | 302 DstReg->WriteMask );
428 if (dst.WriteMask == 0)
450 if (dst.WriteMask & bit) {
[all...] |
| st_cb_drawpixels.c | 90 inst[0].DstReg.WriteMask == WRITEMASK_XYZW &&
236 p->Instructions[ic].DstReg.WriteMask = WRITEMASK_Z;
256 p->Instructions[ic].DstReg.WriteMask = WRITEMASK_Y;
720 dsa.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
725 dsa.depth.writemask = ctx->Depth.Mask;
[all...] |