| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_ureg.c | 252 dst.WriteMask = TGSI_WRITEMASK_XYZW;
907 out[n].dst.WriteMask = dst.WriteMask;
[all...] |
| tgsi_dump.c | 191 uint writemask )
193 if (writemask != TGSI_WRITEMASK_XYZW) {
195 if (writemask & TGSI_WRITEMASK_X)
197 if (writemask & TGSI_WRITEMASK_Y)
199 if (writemask & TGSI_WRITEMASK_Z)
201 if (writemask & TGSI_WRITEMASK_W)
546 _dump_writemask( ctx, dst->Register.WriteMask );
|
| tgsi_text.c | 336 uint *writemask )
344 *writemask = TGSI_WRITEMASK_NONE;
348 *writemask |= TGSI_WRITEMASK_X;
352 *writemask |= TGSI_WRITEMASK_Y;
356 *writemask |= TGSI_WRITEMASK_Z;
360 *writemask |= TGSI_WRITEMASK_W;
363 if (*writemask == TGSI_WRITEMASK_NONE) {
364 report_error( ctx, "Writemask expected" );
371 *writemask = TGSI_WRITEMASK_XYZW;
683 uint writemask; local
1071 uint writemask; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| nv20_context.c | 79 if (buffers & BUFFER_BIT_STENCIL && ctx->Stencil.WriteMask[0])
|
| /external/mesa3d/src/mesa/swrast/ |
| s_drawpix.c | 557 const GLuint stencilMask = ctx->Stencil.WriteMask[0];
|
| s_depth.c | 657 const GLuint writeMask = ctx->Stencil.WriteMask[0];
676 if ((writeMask & stencilMax) != stencilMax) {
698 mask = ((~writeMask) & 0xff) << 24;
699 clear |= (ctx->Stencil.Clear & writeMask & 0xff) << 24;
702 mask = ((~writeMask) & 0xff);
703 clear |= (ctx->Stencil.Clear & writeMask & 0xff);
726 const GLuint sClear = ctx->Stencil.Clear & writeMask;
727 const GLuint sMask = (~writeMask) & 0xff;
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_translate.c | 322 * Compute flags for saturation and writemask.
327 const uint writeMask
328 = inst->Dst[0].Register.WriteMask;
334 if (writeMask & TGSI_WRITEMASK_X)
336 if (writeMask & TGSI_WRITEMASK_Y)
338 if (writeMask & TGSI_WRITEMASK_Z)
340 if (writeMask & TGSI_WRITEMASK_W)
497 uint writemask; local
672 A0_DEST_CHANNEL_ALL, /* dest writemask */
687 A0_DEST_CHANNEL_ALL, /* dest writemask */
[all...] |
| /external/mesa3d/src/mesa/drivers/common/ |
| meta.c | 992 _mesa_StencilMaskSeparate(GL_FRONT, stencil->WriteMask[0]);
1001 _mesa_StencilMaskSeparate(GL_BACK, stencil->WriteMask[1]);
[all...] |
| /external/mesa3d/src/mesa/main/ |
| attrib.c | [all...] |
| ffvertex_prog.c | 546 dst->WriteMask = mask ? mask : WRITEMASK_XYZW;
[all...] |
| mtypes.h | [all...] |
| get.c | [all...] |
| /external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/ |
| sm4_to_tgsi.cpp | 233 return ureg_writemask(_tmp(), d.WriteMask);
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_tgsi.cpp | 139 unsigned int getMask() const { return reg.WriteMask; }
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
223 case TGSI_OPCODE_KIL: /* WriteMask ignored */
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vs_emit.c | 438 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
464 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
493 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
664 dst.dw1.bits.writemask != 0xf)
747 dst.dw1.bits.writemask != 0xf)
824 if (dst.dw1.bits.writemask & WRITEMASK_X) {
847 if (dst.dw1.bits.writemask & WRITEMASK_Y) {
852 if (dst.dw1.bits.writemask & WRITEMASK_Z) {
867 if (dst.dw1.bits.writemask & WRITEMASK_W) {
882 bool need_tmp = (dst.dw1.bits.writemask != 0xf |
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_execute.c | 483 GLuint writeMask = dstReg->WriteMask;
505 if (writeMask & WRITEMASK_X) {
508 writeMask &= ~WRITEMASK_X;
510 if (writeMask & WRITEMASK_Y) {
513 writeMask &= ~WRITEMASK_Y;
515 if (writeMask & WRITEMASK_Z) {
518 writeMask &= ~WRITEMASK_Z;
520 if (writeMask & WRITEMASK_W) {
523 writeMask &= ~WRITEMASK_W
[all...] |
| ir_to_mesa.cpp | 105 dst_reg(gl_register_file file, int writemask)
109 this->writemask = writemask;
118 this->writemask = 0;
127 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:dst_reg
146 this->writemask = WRITEMASK_XYZW;
399 assert(dst.writemask != 0);
435 int done_mask = ~dst.writemask;
469 inst->dst.writemask = this_mask;
513 int done_mask = ~dst.writemask;
[all...] |
| /external/mesa3d/src/gallium/drivers/nv30/ |
| nvfx_fragprog.c | 527 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
[all...] |
| nvfx_vertprog.c | 540 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_state.c | [all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state.c | [all...] |
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_tgsi_insn.c | 111 dest.mask = reg->Register.WriteMask;
924 writemask(temp, channel),
1052 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 ))
1075 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0))
1100 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 ))
[all...] |
