| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb32.s | 773 addw r9, r0, #0
774 addw r6, pc, #0xfff
|
| thumb2_bad_reg.l | 14 [^:]*:[0-9]+: Error: r13 not allowed here -- `addw r13,r0,#1'
15 [^:]*:[0-9]+: Error: r15 not allowed here -- `addw r15,r0,#1'
24 [^:]*:[0-9]+: Error: r15 not allowed here -- `addw r15,r13,#1'
[all...] |
| thumb32.d | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| opcode-suffix.d | 406 *[0-9a-f]+: 66 01 90 90 90 90 90[ ]+addw[ ]+%dx,-0x6f6f6f70\(%eax\)
407 *[0-9a-f]+: 66 03 90 90 90 90 90[ ]+addw[ ]+-0x6f6f6f70\(%eax\),%dx
408 *[0-9a-f]+: 66 05 90 90[ ]+addw[ ]+\$0x9090,%ax
|
| /external/valgrind/none/tests/x86/ |
| insn_basic.def | 67 addw imm8[12] r16.uw[3456] => 1.uw[3468]
68 addw imm16[1234] ax.uw[5678] => 1.uw[6912]
69 addw imm16[1234] bx.uw[5678] => 1.uw[6912]
70 addw imm16[1234] m16.uw[5678] => 1.uw[6912]
71 addw r16.uw[1234] r16.uw[5678] => 1.uw[6912]
72 addw r16.uw[1234] m16.uw[5678] => 1.uw[6912]
73 addw m16.uw[1234] r16.uw[5678] => 1.uw[6912]
[all...] |
| /external/llvm/test/MC/X86/ |
| x86-32-coverage.s | 323 // CHECK: addw $31438, 3735928559(%ebx,%ecx,8)
325 addw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
327 // CHECK: addw $31438, 69
329 addw $0x7ace,0x45
331 // CHECK: addw $31438, 32493
333 addw $0x7ace,0x7eed
335 // CHECK: addw $31438, 3133065982
337 addw $0x7ace,0xbabecafe
339 // CHECK: addw $31438, 305419896
341 addw $0x7ace,0x1234567
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/X86/ |
| x86-32-coverage.s | 45 // CHECK: addw $31438, 3735928559(%ebx,%ecx,8)
46 addw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | 73 addw r2, r3, #257
75 addw r12, r6, #0x100
86 addw r2, #-16
87 addw r2, #-16
88 addw r2, r2, #-16
96 @ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12]
97 @ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12]
99 @ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c]
181 addw r6, sp, #1020 // T4
182 @ CHECK: addw r6, sp, #1020 @ encoding: [0x0d,0xf2,0xfc,0x36
[all...] |
| /external/valgrind/none/tests/arm/ |
| v6intThumb.stdout.exp | [all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb2-instructions.s | 72 addw r2, r3, #257
74 addw r12, r6, #0x100
83 @ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12]
84 @ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12]
86 @ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c]
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-pc-operand-imm12-t32.cc | 53 M(addw) \
[all...] |
| test-assembler-cond-rd-rn-operand-imm12-t32.cc | 53 M(addw) \
[all...] |
| /external/mesa3d/src/mesa/x86/ |
| assyntax.h | 388 #define ADD_W(a, b) CHOICE(addw ARG2(a,b), addw ARG2(a,b), _WTOG add ARG2(b,a))
[all...] |
| /external/valgrind/perf/ |
| tinycc.c | [all...] |
| /external/vixl/src/aarch32/ |
| assembler-aarch32.h | 1924 void addw(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.h | 506 void addw(Condition cond, Register rd, Register rn, const Operand& operand);
[all...] |
| disasm-aarch32.cc | 1183 void Disassembler::addw(Condition cond, function in class:vixl::aarch32::Disassembler
[all...] |
| assembler-aarch32.cc | 2377 void Assembler::addw(Condition cond, function in class:vixl::aarch32::Assembler
[all...] |
