| /external/google-breakpad/src/testing/test/ |
| gmock-generated-actions_test.cc | 140 const char* s7) {
141 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7;
146 const char* s7, const char* s8) {
147 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8;
152 const char* s7, const char* s8, const char* s9) {
153 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8 + s9;
158 const char* s7, const char* s8, const char* s9,
160 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8 + s9 + s10;
[all...] |
| /external/googletest/googlemock/test/ |
| gmock-generated-actions_test.cc | 140 const char* s7) {
141 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7;
146 const char* s7, const char* s8) {
147 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8;
152 const char* s7, const char* s8, const char* s9) {
153 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8 + s9;
158 const char* s7, const char* s8, const char* s9,
160 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8 + s9 + s10;
[all...] |
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64.s | 20 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 24 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| simple-fp-encoding.s | 226 @ CHECK: vldmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x91,0xec]
228 vldmia r1, {s2,s3-s6,s7}
231 @ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec]
233 vstmia r1, {s2,s3-s6,s7}
|
| /external/v8/src/compiler/ |
| c-linkage.cc | 97 s7.bit()
108 s7.bit()
|
| /external/v8/testing/gmock/test/ |
| gmock-generated-actions_test.cc | 140 const char* s7) {
141 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7;
146 const char* s7, const char* s8) {
147 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8;
152 const char* s7, const char* s8, const char* s9) {
153 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8 + s9;
158 const char* s7, const char* s8, const char* s9,
160 return string(s1) + s2 + s3 + s4 + s5 + s6 + s7 + s8 + s9 + s10;
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 20 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
39 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 24 dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
49 ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
60 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/none/tests/arm/ |
| vfpv4_fma.stdout.exp | 27 vfma.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
38 vfma.f32 s29, s15, s7 :: Qd 0x55555555 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
44 vfma.f32 s29, s25, s7 :: Qd 0x55555555 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
76 vfms.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
87 vfms.f32 s29, s15, s7 :: Qd 0x55555555 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
93 vfms.f32 s29, s25, s7 :: Qd 0x55555555 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
125 vfnma.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
136 vfnma.f32 s29, s15, s7 :: Qd 0x55555555 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
142 vfnma.f32 s29, s25, s7 :: Qd 0x55555555 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
174 vfnms.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc0000
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| vfp1xD.d | 163 0+264 <[^>]*> eef53a40 (vcmp\.f32 s7, #0.0|fcmpzs s7)
189 0+2cc <[^>]*> 0ef41ae3 (vcmpeeq\.f32|fcmpeseq) s3, s7
196 0+2e8 <[^>]*> 0ef12ae3 (vsqrteq\.f32|fsqrtseq) s5, s7
209 0+31c <[^>]*> 0cd23a01 (vldmiaeq|fldmiaseq) r2, {s7}
|
| /art/runtime/arch/mips/ |
| quick_entrypoints_mips.S | 54 sw $s7, 80($sp)
113 sw $s7, 32($sp)
145 lw $s7, 32($sp)
188 sw $s7, 96($sp)
266 lw $s7, 96($sp)
302 * Callee-save: $at, $v0-$v1, $a0-$a3, $t0-$t7, $s0-$s7, $t8-$t9, $gp, $fp $ra, $f0-$f31;
325 sw $s7, 232($sp)
411 * Callee-save: $at, $v0-$v1, $a0-$a3, $t0-$t7, $s0-$s7, $t8-$t9, $gp, $fp $ra, $f0-$f31;
455 lw $s7, 232($sp)
571 sw $s7, 32($sp
[all...] |
| /external/valgrind/none/tests/mips32/ |
| branches.c | 268 TESTINST1(21, s7);
294 TESTINST2(21, s7);
320 TESTINST3(21, s7);
670 TESTINST3j(21, s7);
696 TESTINST3ja(21, s7);
|
| /external/llvm/test/MC/ARM/ |
| simple-fp-encoding.s | 15 vdiv.f32 s5, s7
20 @ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee]
289 @ CHECK: vldmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x91,0xec]
291 vldmia r1, {s2,s3-s6,s7}
294 @ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec]
297 vstmia r1, {s2,s3-s6,s7}
|
| /external/tremolo/Tremolo/ |
| mdct.c | 113 REG_TYPE s7 = x[6] - x[7]; local
116 x[1] = s7 - s1;
118 x[3] = s7 + s1;
|
| mdctLARM.s | 818 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7]
822 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1
823 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1
847 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7]
851 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1
852 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1
934 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7]
938 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1
939 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1
963 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| highbd_idct32x32_1024_add_neon.c | 130 int32x4x2_t *const s5, int32x4x2_t *const s6, int32x4x2_t *const s7) {
152 s7->val[0] = vld1q_s32(in);
153 s7->val[1] = vld1q_s32(in + 4);
199 int32x4x2_t s0, s1, s2, s3, s4, s5, s6, s7; local
202 load_s32x4q_dual(input, &s0, &s1, &s2, &s3, &s4, &s5, &s6, &s7);
203 transpose_and_store_s32_8x8(s0, s1, s2, s3, s4, s5, s6, s7, &t_buf);
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 26 dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
53 ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /bionic/libc/arch-mips/bionic/ |
| setjmp.S | 254 m_mangle_reg_and_store s7, t0, t3, SC_REGS+8*REGSZ(a0)
371 m_unmangle_reg_and_load s7, t0, t3, SC_REGS+8*REGSZ(a0)
|
| /bionic/libm/upstream-freebsd/lib/msun/ld128/ |
| e_lgammal_r.c | 145 s7 = 3.70262021550340817867688714880797019e-03L, variable
302 p = y*(s0+y*(s1+y*(s2+y*(s3+y*(s4+y*(s5+y*(s6+y*(s7+y*(s8+
|
| /external/clang/test/OpenMP/ |
| distribute_parallel_for_private_messages.cpp | 80 class S7 : public T {
82 S7() : a(0) {}
85 S7(T v) : a(v) {
92 S7 &operator=(S7 &s) {
215 S7<S6<float> > s7(0.0) , s7_0(1.0);
312 s7 = s7_0; // expected-note {{in instantiation of member function 'S7<S6<float> >::operator=' requested here}}
|
| distribute_parallel_for_simd_private_messages.cpp | 80 class S7 : public T {
82 S7() : a(0) {}
85 S7(T v) : a(v) {
92 S7 &operator=(S7 &s) {
215 S7<S6<float> > s7(0.0) , s7_0(1.0);
312 s7 = s7_0; // expected-note {{in instantiation of member function 'S7<S6<float> >::operator=' requested here}}
|
| distribute_simd_private_messages.cpp | 80 class S7 : public T {
82 S7() : a(0) {}
85 S7(T v) : a(v) {
92 S7 &operator=(S7 &s) {
215 S7<S6<float> > s7(0.0) , s7_0(1.0);
312 s7 = s7_0; // expected-note {{in instantiation of member function 'S7<S6<float> >::operator=' requested here}}
|
| /external/google-breakpad/src/common/android/ |
| breakpad_getcontext.S | 289 sw s7, (23 * MCONTEXT_REG_SIZE + MCONTEXT_GREGS_OFFSET)(a0)
367 sd s7, (23 * MCONTEXT_REG_SIZE + MCONTEXT_GREGS_OFFSET)(a0)
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 14 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
