/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 398 addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass); 440 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 442 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); [all...] |
SPUISelDAGToDAG.cpp | 601 case MVT::v4f32: [all...] |
/external/llvm/lib/Target/X86/InstPrinter/ |
X86InstComments.cpp | 489 DecodeInsertElementMask(MVT::v4f32, 2, 2, ShuffleMask); 505 DecodeInsertElementMask(MVT::v4f32, 0, 2, ShuffleMask); 894 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 350 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 355 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 360 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 366 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); [all...] |
/external/llvm/utils/TableGen/ |
CodeGenTarget.cpp | 117 case MVT::v4f32: return "MVT::v4f32";
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/external/mesa3d/src/gallium/drivers/radeon/ |
R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
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SIISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
CodeGenTarget.cpp | 86 case MVT::v4f32: return "MVT::v4f32";
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/prebuilts/clang/host/darwin-x86/clang-3688880/lib64/clang/4.0/include/ |
msa.h | 44 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
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/prebuilts/clang/host/darwin-x86/clang-3859424/lib64/clang/4.0/include/ |
msa.h | 44 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
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/prebuilts/clang/host/linux-x86/clang-3688880/lib64/clang/4.0/include/ |
msa.h | 44 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
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/prebuilts/clang/host/linux-x86/clang-3859424/lib64/clang/4.0/include/ |
msa.h | 44 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMISelDAGToDAG.cpp | [all...] |
ARMISelLowering.cpp | 451 addQRTypeForNEON(MVT::v4f32); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 71 case MVT::v4f32: 216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); 218 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600ISelLowering.cpp | 40 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); 169 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 174 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 739 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); [all...] |
SIISelLowering.cpp | 72 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass); 127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom); [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 109 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass); 286 // as such. In particular, we can do these for v4f32 even though there 381 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); 386 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 93 addQRTypeForNEON(MVT::v4f32); 297 // v4f16 is also a storage-only type, so promote it to v4f32 when that is 305 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32); 306 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32); 307 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32); 308 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32); 309 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); 310 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); 575 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16 621 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) [all...] |
/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | 400 case MVT::v4f32: 550 case MVT::v4f32: [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | [all...] |
MipsSEISelLowering.cpp | 92 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); [all...] |