| /external/libvpx/libvpx/vpx_dsp/x86/ |
| inv_wht_sse2.asm | 55 pshufd m1, m0, 0x0e
56 pshufd m3, m2, 0x0e
67 pshufd m1, m0, 0x0e
68 pshufd m3, m2, 0x0e
|
| /external/llvm/test/MC/ARM/ |
| neont2-cmp-encoding.s | 25 @ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0e]
27 @ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0e]
33 @ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0e]
35 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e]
|
| neont2-convert-encoding.s | 25 @ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0e]
27 @ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0e]
33 @ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0e]
35 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e]
|
| neon-convert-encoding.s | 27 @ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
31 @ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
43 @ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2]
47 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neon-convert-encoding.s | 23 @ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
25 @ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
31 @ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2]
33 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
|
| neont2-cmp-encoding.s | 25 @ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0e]
27 @ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0e]
33 @ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0e]
35 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e]
|
| neont2-convert-encoding.s | 25 @ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0e]
27 @ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0e]
33 @ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0e]
35 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e]
|
| neon-cmp-encoding.s | 15 @ CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2]
19 @ CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2]
44 @ CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3]
51 @ CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3]
52 @ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3]
53 @ CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3]
78 @ CHECK: vcgt.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x60,0xf3]
85 @ CHECK: vcgt.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x60,0xf3]
86 @ CHECK: vacgt.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x60,0xf3]
87 @ CHECK: vacgt.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x60,0xf3
[all...] |
| /external/webrtc/webrtc/modules/rtp_rtcp/source/ |
| h264_bitstream_parser_unittest.cc | 27 0x75, 0x67, 0xad, 0x41, 0x64, 0x24, 0x0e, 0xa0, 0xb2, 0x12, 0x1e, 0xf8,
32 0x00, 0x00, 0x00, 0x01, 0x41, 0xe2, 0x01, 0x16, 0x0e, 0x3e, 0x2b, 0x86,
|
| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-rn-rm-a32-mul.h | 125 0x9b, 0x0d, 0x0e, 0x20 // mul cs r14 r11 r13
134 0x9c, 0x0e, 0x07, 0x20 // mul cs r7 r12 r14
179 0x97, 0x02, 0x0e, 0xe0 // mul al r14 r7 r2
218 0x9e, 0x0e, 0x0b, 0x10 // mul ne r11 r14 r14
224 0x98, 0x02, 0x0e, 0xd0 // mul le r14 r8 r2
233 0x95, 0x0e, 0x04, 0x50 // mul pl r4 r5 r14
248 0x9b, 0x08, 0x0e, 0x70 // mul vc r14 r11 r8
254 0x91, 0x0e, 0x02, 0x00 // mul eq r2 r1 r14
257 0x94, 0x0e, 0x09, 0x00 // mul eq r9 r4 r14
266 0x9b, 0x0e, 0x09, 0xd0 // mul le r9 r11 r1
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h | 41 0x0d, 0xa5, 0x0e, 0x40 // and_ mi r10 r14 r13 LSL 10
53 0xe7, 0x33, 0x0e, 0xa0 // and_ ge r3 r14 r7 ROR 7
65 0x08, 0xe2, 0x0e, 0xa0 // and_ ge r14 r14 r8 LSL 4
107 0x00, 0x8d, 0x0e, 0x00 // and_ eq r8 r14 r0 LSL 26
110 0xe7, 0xb1, 0x0e, 0x20 // and_ cs r11 r14 r7 ROR 3
125 0x8c, 0x7c, 0x0e, 0x10 // and_ ne r7 r14 r12 LSL 25
161 0x80, 0x1c, 0x0e, 0xa0 // and_ ge r1 r14 r0 LSL 25
176 0x89, 0xa1, 0x0e, 0x20 // and_ cs r10 r14 r9 LSL 3
191 0x68, 0xeb, 0x0e, 0xc0 // and_ gt r14 r14 r8 ROR 22
257 0xe9, 0x4a, 0x0e, 0x90 // and_ ls r4 r14 r9 ROR 2
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h | 47 0x06, 0xeb, 0x1a, 0x0e // add al r14 r6 r10 LSR 32
83 0x0e, 0xeb, 0xae, 0x42 // add al r2 r14 r14 ASR 18
89 0x0e, 0xeb, 0x97, 0x41 // add al r1 r14 r7 LSR 18
95 0x05, 0xeb, 0x5c, 0x0e // add al r14 r5 r12 LSR 1
113 0x0e, 0xeb, 0x1b, 0x6b // add al r11 r14 r11 LSR 24
119 0x0d, 0xeb, 0x6a, 0x0e // add al r14 r13 r10 ASR 1
128 0x0e, 0xeb, 0xd5, 0x68 // add al r8 r14 r5 LSR 27
131 0x0e, 0xeb, 0x6d, 0x59 // add al r9 r14 r13 ASR 21
134 0x0e, 0xeb, 0xee, 0x0b // add al r11 r14 r14 ASR 3
182 0x0e, 0xeb, 0x1d, 0x17 // add al r7 r14 r13 LSR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h | 47 0x06, 0xea, 0x1a, 0x0e // and_ al r14 r6 r10 LSR 32
83 0x0e, 0xea, 0xae, 0x42 // and_ al r2 r14 r14 ASR 18
89 0x0e, 0xea, 0x97, 0x41 // and_ al r1 r14 r7 LSR 18
95 0x05, 0xea, 0x5c, 0x0e // and_ al r14 r5 r12 LSR 1
113 0x0e, 0xea, 0x1b, 0x6b // and_ al r11 r14 r11 LSR 24
119 0x0d, 0xea, 0x6a, 0x0e // and_ al r14 r13 r10 ASR 1
128 0x0e, 0xea, 0xd5, 0x68 // and_ al r8 r14 r5 LSR 27
131 0x0e, 0xea, 0x6d, 0x59 // and_ al r9 r14 r13 ASR 21
134 0x0e, 0xea, 0xee, 0x0b // and_ al r11 r14 r14 ASR 3
182 0x0e, 0xea, 0x1d, 0x17 // and_ al r7 r14 r13 LSR
[all...] |
| assembler-cond-rd-operand-const-a32-can-use-pc-cmn.h | 110 0xff, 0x0e, 0x7c, 0x63 // cmn vs r12 0x00000ff0
197 0xab, 0x0e, 0x77, 0xc3 // cmn gt r7 0x00000ab0
260 0xff, 0x0e, 0x74, 0xc3 // cmn gt r4 0x00000ff0
296 0xab, 0x0e, 0x78, 0x03 // cmn eq r8 0x00000ab0
329 0xff, 0x0e, 0x7f, 0x13 // cmn ne r15 0x00000ff0
344 0xab, 0x0e, 0x76, 0x53 // cmn pl r6 0x00000ab0
350 0xab, 0x0e, 0x74, 0x43 // cmn mi r4 0x00000ab0
362 0xab, 0x0e, 0x7d, 0xa3 // cmn ge r13 0x00000ab0
368 0xab, 0x0e, 0x7b, 0xb3 // cmn lt r11 0x00000ab0
380 0xff, 0x0e, 0x74, 0x33 // cmn cc r4 0x00000ff
[all...] |
| assembler-cond-rd-operand-const-a32-can-use-pc-cmp.h | 110 0xff, 0x0e, 0x5c, 0x63 // cmp vs r12 0x00000ff0
197 0xab, 0x0e, 0x57, 0xc3 // cmp gt r7 0x00000ab0
260 0xff, 0x0e, 0x54, 0xc3 // cmp gt r4 0x00000ff0
296 0xab, 0x0e, 0x58, 0x03 // cmp eq r8 0x00000ab0
329 0xff, 0x0e, 0x5f, 0x13 // cmp ne r15 0x00000ff0
344 0xab, 0x0e, 0x56, 0x53 // cmp pl r6 0x00000ab0
350 0xab, 0x0e, 0x54, 0x43 // cmp mi r4 0x00000ab0
362 0xab, 0x0e, 0x5d, 0xa3 // cmp ge r13 0x00000ab0
368 0xab, 0x0e, 0x5b, 0xb3 // cmp lt r11 0x00000ab0
380 0xff, 0x0e, 0x54, 0x33 // cmp cc r4 0x00000ff
[all...] |
| assembler-cond-rd-operand-const-a32-can-use-pc-teq.h | 110 0xff, 0x0e, 0x3c, 0x63 // teq vs r12 0x00000ff0
197 0xab, 0x0e, 0x37, 0xc3 // teq gt r7 0x00000ab0
260 0xff, 0x0e, 0x34, 0xc3 // teq gt r4 0x00000ff0
296 0xab, 0x0e, 0x38, 0x03 // teq eq r8 0x00000ab0
329 0xff, 0x0e, 0x3f, 0x13 // teq ne r15 0x00000ff0
344 0xab, 0x0e, 0x36, 0x53 // teq pl r6 0x00000ab0
350 0xab, 0x0e, 0x34, 0x43 // teq mi r4 0x00000ab0
362 0xab, 0x0e, 0x3d, 0xa3 // teq ge r13 0x00000ab0
368 0xab, 0x0e, 0x3b, 0xb3 // teq lt r11 0x00000ab0
380 0xff, 0x0e, 0x34, 0x33 // teq cc r4 0x00000ff
[all...] |
| assembler-cond-rd-operand-const-a32-can-use-pc-tst.h | 110 0xff, 0x0e, 0x1c, 0x63 // tst vs r12 0x00000ff0
197 0xab, 0x0e, 0x17, 0xc3 // tst gt r7 0x00000ab0
260 0xff, 0x0e, 0x14, 0xc3 // tst gt r4 0x00000ff0
296 0xab, 0x0e, 0x18, 0x03 // tst eq r8 0x00000ab0
329 0xff, 0x0e, 0x1f, 0x13 // tst ne r15 0x00000ff0
344 0xab, 0x0e, 0x16, 0x53 // tst pl r6 0x00000ab0
350 0xab, 0x0e, 0x14, 0x43 // tst mi r4 0x00000ab0
362 0xab, 0x0e, 0x1d, 0xa3 // tst ge r13 0x00000ab0
368 0xab, 0x0e, 0x1b, 0xb3 // tst lt r11 0x00000ab0
380 0xff, 0x0e, 0x14, 0x33 // tst cc r4 0x00000ff
[all...] |
| assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h | 47 0xe2, 0x0e, 0x70, 0xb1 // cmn lt r0 r2 ROR 29
53 0x81, 0x0e, 0x77, 0x81 // cmn hi r7 r1 LSL 29
149 0x0e, 0x09, 0x7a, 0xe1 // cmn al r10 r14 LSL 18
215 0xe8, 0x0e, 0x74, 0xa1 // cmn ge r4 r8 ROR 29
251 0x67, 0x0e, 0x75, 0x61 // cmn vs r5 r7 ROR 28
278 0x0e, 0x0c, 0x7d, 0x81 // cmn hi r13 r14 LSL 24
341 0x85, 0x0e, 0x77, 0x61 // cmn vs r7 r5 LSL 29
356 0x0e, 0x06, 0x71, 0x41 // cmn mi r1 r14 LSL 12
395 0x84, 0x0e, 0x72, 0xc1 // cmn gt r2 r4 LSL 29
398 0x09, 0x0e, 0x7b, 0xd1 // cmn le r11 r9 LSL 2
[all...] |
| assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h | 47 0xe2, 0x0e, 0x50, 0xb1 // cmp lt r0 r2 ROR 29
53 0x81, 0x0e, 0x57, 0x81 // cmp hi r7 r1 LSL 29
149 0x0e, 0x09, 0x5a, 0xe1 // cmp al r10 r14 LSL 18
215 0xe8, 0x0e, 0x54, 0xa1 // cmp ge r4 r8 ROR 29
251 0x67, 0x0e, 0x55, 0x61 // cmp vs r5 r7 ROR 28
278 0x0e, 0x0c, 0x5d, 0x81 // cmp hi r13 r14 LSL 24
341 0x85, 0x0e, 0x57, 0x61 // cmp vs r7 r5 LSL 29
356 0x0e, 0x06, 0x51, 0x41 // cmp mi r1 r14 LSL 12
395 0x84, 0x0e, 0x52, 0xc1 // cmp gt r2 r4 LSL 29
398 0x09, 0x0e, 0x5b, 0xd1 // cmp le r11 r9 LSL 2
[all...] |
| assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h | 47 0xe2, 0x0e, 0x30, 0xb1 // teq lt r0 r2 ROR 29
53 0x81, 0x0e, 0x37, 0x81 // teq hi r7 r1 LSL 29
149 0x0e, 0x09, 0x3a, 0xe1 // teq al r10 r14 LSL 18
215 0xe8, 0x0e, 0x34, 0xa1 // teq ge r4 r8 ROR 29
251 0x67, 0x0e, 0x35, 0x61 // teq vs r5 r7 ROR 28
278 0x0e, 0x0c, 0x3d, 0x81 // teq hi r13 r14 LSL 24
341 0x85, 0x0e, 0x37, 0x61 // teq vs r7 r5 LSL 29
356 0x0e, 0x06, 0x31, 0x41 // teq mi r1 r14 LSL 12
395 0x84, 0x0e, 0x32, 0xc1 // teq gt r2 r4 LSL 29
398 0x09, 0x0e, 0x3b, 0xd1 // teq le r11 r9 LSL 2
[all...] |
| assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h | 47 0xe2, 0x0e, 0x10, 0xb1 // tst lt r0 r2 ROR 29
53 0x81, 0x0e, 0x17, 0x81 // tst hi r7 r1 LSL 29
149 0x0e, 0x09, 0x1a, 0xe1 // tst al r10 r14 LSL 18
215 0xe8, 0x0e, 0x14, 0xa1 // tst ge r4 r8 ROR 29
251 0x67, 0x0e, 0x15, 0x61 // tst vs r5 r7 ROR 28
278 0x0e, 0x0c, 0x1d, 0x81 // tst hi r13 r14 LSL 24
341 0x85, 0x0e, 0x17, 0x61 // tst vs r7 r5 LSL 29
356 0x0e, 0x06, 0x11, 0x41 // tst mi r1 r14 LSL 12
395 0x84, 0x0e, 0x12, 0xc1 // tst gt r2 r4 LSL 29
398 0x09, 0x0e, 0x1b, 0xd1 // tst le r11 r9 LSL 2
[all...] |
| /external/kernel-headers/modified/scsi/ |
| scsi_proto.h | 137 #define MI_REPORT_PRIORITY 0x0e
146 #define MO_SET_PRIORITY 0x0e
243 #define MISCOMPARE 0x0e
264 #define TYPE_RBC 0x0e
299 #define SCSI_ACCESS_STATE_OFFLINE 0x0e
|
| /external/kernel-headers/original/scsi/ |
| scsi_proto.h | 136 #define MI_REPORT_PRIORITY 0x0e
145 #define MO_SET_PRIORITY 0x0e
241 #define MISCOMPARE 0x0e
262 #define TYPE_RBC 0x0e
295 #define SCSI_ACCESS_STATE_OFFLINE 0x0e
|
| /external/sonivox/jet_tools/JetCreator/ |
| img_Undo.py | 20 "\x80@\xff\xcf\x00\x9a\xf7\xf2|h\xda\x827+k_,,,\x0e\x8b)\xee\xde\x0f\xcc\xba\
24 \xa2\x82\xd2yB\xa6Z\xd1*\x0e\x98\x8c\xec\x9c@ \xcc\x80A\xcf\x91}D\x11t)\xc5\
28 \xd9S:\xab\xf6\xbe\x85\xcb\x9f\niy\x1e\xed\xf5\x02\xa0\xf1@\xbb\xa3\x00\x0e(\
58 \x01`L\xc0\x05Y0\xb1XF\xd8o\xd5\xd3\x1bX\x1b\x0e[N _u\xf4v\x0fN\x8b\x0c\xd9G\
66 \xb9\x0e\x92\tUA\x8e\xb1c\x13\xd1\x17\xccn=\xb2\xce\xefk\xbd[\x8f\x0706f\xac\
|
| /packages/inputmethods/OpenWnn/libs/libwnnJpnDic/ |
| WnnJpnDic.c | 24 0x00, 0x00, 0x00, 0x00, 0x01, 0x8a, 0x4e, 0x02, 0x00, 0x00, 0x02, 0x26, 0x10, 0x0e, 0x00, 0x00,
25 0x00, 0xac, 0x00, 0xbe, 0x00, 0x0b, 0x00, 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x10,
41 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
78 0xf2, 0x43, 0x80, 0x20, 0x0e, 0x31, 0x00, 0x20, 0x0e, 0xc1, 0x10, 0x47, 0xf0, 0x84, 0x80, 0x20,
129 0x6a, 0x0e, 0x80, 0x48, 0x6b, 0x8f, 0x00, 0x48, 0x6d, 0x8f, 0x40, 0x48, 0x6e, 0xcf, 0xc0, 0x48,
149 0x48, 0x9c, 0xc8, 0x40, 0x21, 0x82, 0x42, 0x20, 0x48, 0xa4, 0x0f, 0x00, 0x68, 0xa4, 0x06, 0x0e,
237 0x97, 0x0e, 0x80, 0x69, 0x97, 0x0d, 0xd1, 0x0f, 0x00, 0x49, 0x98, 0x8f, 0x40, 0x49, 0x99, 0x8f,
240 0xa0, 0xd2, 0x00, 0x69, 0xa2, 0x0e, 0x19, 0x52, 0x40, 0x69, 0xa1, 0xce, 0x1e, 0x92, 0xc0, 0x49,
260 0x00, 0x49, 0xd8, 0x0e, 0xc0, 0x49, 0xd8, 0x4f, 0x00, 0x69, 0xd8, 0xcf, 0xd7, 0xcf, 0x40, 0x49
[all...] |
