| /external/llvm/test/CodeGen/AMDGPU/ |
| mad_int24.ll | 17 %a_24 = ashr i32 %0, 8
20 %2 = mul i32 %a_24, %b_24
|
| mul_int24.ll | 17 %a_24 = ashr i32 %0, 8
20 %2 = mul i32 %a_24, %b_24
|
| mul_uint24.ll | 13 %a_24 = lshr i32 %0, 8
16 %2 = mul i32 %a_24, %b_24
63 %a_24 = lshr i64 %tmp0, 40
66 %tmp2 = mul i64 %a_24, %b_24
|
| mad_uint24.ll | 13 %a_24 = lshr i32 %0, 8
16 %2 = mul i32 %a_24, %b_24
|
| /external/webrtc/webrtc/modules/audio_processing/aec/ |
| aec_rdft_neon.c | 90 const float32x2_t a_24 = vld1_f32(&a[j + 24]); local
94 const float32x4_t a_24_56 = vcombine_f32(a_24, a_56);
148 const float32x2_t a_24 = vld1_f32(&a[j + 24]); local
152 const float32x4_t a_24_56 = vcombine_f32(a_24, a_56);
|
| aec_rdft_sse2.c | 102 const __m128i a_24 = _mm_loadl_epi64((__m128i*)&a[j0 + 24]); local
108 const __m128 a_24_56 = _mm_shuffle_ps(_mm_castsi128_ps(a_24),
176 const __m128i a_24 = _mm_loadl_epi64((__m128i*)&a[j0 + 24]); local
182 const __m128 a_24_56 = _mm_shuffle_ps(_mm_castsi128_ps(a_24),
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| s390-opc.c | 125 #define A_24 33 /* Access reg. starting at position 24 */
319 #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
320 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
[all...] |
