| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 770 TEST_F(AssemblerMIPSTest, Addiu32) {
771 __ Addiu32(mips::A1, mips::A2, -0x8000);
772 __ Addiu32(mips::A1, mips::A2, +0);
773 __ Addiu32(mips::A1, mips::A2, +0x7FFF);
774 __ Addiu32(mips::A1, mips::A2, -0x10000);
775 __ Addiu32(mips::A1, mips::A2, -0x8001);
776 __ Addiu32(mips::A1, mips::A2, +0x8000);
777 __ Addiu32(mips::A1, mips::A2, +0xFFFE);
778 __ Addiu32(mips::A1, mips::A2, -0x10001);
779 __ Addiu32(mips::A1, mips::A2, +0xFFFF)
[all...] |
| assembler_mips.cc | [all...] |
| assembler_mips.h | 472 void Addiu32(Register rt, Register rs, int32_t value, Register rtmp = AT);
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| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | [all...] |
| assembler_mips64.h | 758 void Addiu32(GpuRegister rt, GpuRegister rs, int32_t value);
[all...] |
| assembler_mips64.cc | [all...] |
| /art/compiler/optimizing/ |
| intrinsics_mips.cc | [all...] |
| code_generator_mips.cc | [all...] |
| code_generator_mips64.cc | 766 // art::mips64::MipsAssembler::Addiu32 below), but it has
[all...] |
| intrinsics_mips64.cc | [all...] |
